linux-kernel - Re: [PATCH v4 2/2] arm64: dts: cix: Add OrangePi 6 Plus board support

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Message-ID: <aWRLSNke_flVURY6@nchen-desktop>
Date: Mon, 12 Jan 2026 09:15:52 +0800
From: Peter Chen <peter.chen@...tech.com>
To: Gary Yang <gary.yang@...tech.com>
Cc: <fugang.duan@...tech.com>, <robh@...nel.org>, <krzk+dt@...nel.org>,
	<conor+dt@...nel.org>, <cix-kernel-upstream@...tech.com>,
	<linux-arm-kernel@...ts.infradead.org>,
	<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4 2/2] arm64: dts: cix: Add OrangePi 6 Plus board support

On 26-01-10 17:34:06, Gary Yang wrote:
> OrangePi 6 Plus adopts CIX CD8180/CD8160 SoC, built-in 12-core 64-bit
> processor + NPU processor,integrated graphics processor, equipped with
> 16GB/32GB/64GB LPDDR5, and provides two M.2 KEY-M interfaces 2280 for NVMe
> SSD,as well as SPI FLASH and TF slots to meet the needs of fast read/write
> and high-capacity storage
> 
> Signed-off-by: Gary Yang <gary.yang@...tech.com>

Applied, Thanks.

Peter
> ---
>  arch/arm64/boot/dts/cix/Makefile     |  1 +
>  arch/arm64/boot/dts/cix/sky1-xcp.dts | 83 ++++++++++++++++++++++++++++
>  2 files changed, 84 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/cix/sky1-xcp.dts
> 
> diff --git a/arch/arm64/boot/dts/cix/Makefile b/arch/arm64/boot/dts/cix/Makefile
> index ed3713982012..8a6c6fdc4ec0 100644
> --- a/arch/arm64/boot/dts/cix/Makefile
> +++ b/arch/arm64/boot/dts/cix/Makefile
> @@ -1,2 +1,3 @@
>  # SPDX-License-Identifier: GPL-2.0
>  dtb-$(CONFIG_ARCH_CIX) += sky1-orion-o6.dtb
> +dtb-$(CONFIG_ARCH_CIX) += sky1-xcp.dtb
> diff --git a/arch/arm64/boot/dts/cix/sky1-xcp.dts b/arch/arm64/boot/dts/cix/sky1-xcp.dts
> new file mode 100644
> index 000000000000..1fae52dc9bb0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/cix/sky1-xcp.dts
> @@ -0,0 +1,83 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright 2025 Cix Technology Group Co., Ltd.
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include "sky1.dtsi"
> +#include "sky1-pinfunc.h"
> +
> +/ {
> +	model = "Xunlong,OrangePi 6 Plus";
> +	compatible = "xunlong,orangepi-6-plus", "cix,sky1";
> +
> +	aliases {
> +		serial2 = &uart2;
> +	};
> +
> +	chosen {
> +		stdout-path = &uart2;
> +	};
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		linux,cma {
> +			compatible = "shared-dma-pool";
> +			reusable;
> +			size = <0x0 0x28000000>;
> +			linux,cma-default;
> +		};
> +	};
> +
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_hog>;
> +
> +	pinctrl_hog: hog-cfg {
> +		pins {
> +			pinmux = <CIX_PAD_GPIO144_FUNC_GPIO144>,
> +				<CIX_PAD_GPIO145_FUNC_GPIO145>,
> +				<CIX_PAD_GPIO146_FUNC_GPIO146>,
> +				<CIX_PAD_GPIO147_FUNC_GPIO147>;
> +			bias-pull-down;
> +			drive-strength = <8>;
> +		};
> +	};
> +};
> +
> +&iomuxc_s5 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_hog_s5>;
> +
> +	pinctrl_hog_s5: hog-s5-cfg {
> +		pins {
> +			pinmux = <CIX_PAD_GPIO014_FUNC_GPIO014>;
> +			bias-pull-up;
> +			drive-strength = <8>;
> +
> +		};
> +	};
> +};
> +
> +&pcie_x8_rc {
> +	status = "okay";
> +};
> +
> +&pcie_x2_rc {
> +	status = "okay";
> +};
> +
> +&pcie_x1_1_rc {
> +	status = "okay";
> +};
> +
> +&uart2 {
> +	status = "okay";
> +};
> -- 
> 2.49.0
> 

-- 

Best regards,
Peter