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Message-Id: <DFMH8W40TCJ0.XCTHNRJFJE4T@fairphone.com>
Date: Mon, 12 Jan 2026 09:45:01 +0100
From: "Luca Weiss" <luca.weiss@...rphone.com>
To: "Neil Armstrong" <neil.armstrong@...aro.org>, "Luca Weiss"
<luca.weiss@...rphone.com>, "Herbert Xu" <herbert@...dor.apana.org.au>,
"David S. Miller" <davem@...emloft.net>, "Rob Herring" <robh@...nel.org>,
"Krzysztof Kozlowski" <krzk+dt@...nel.org>, "Conor Dooley"
<conor+dt@...nel.org>, "Bjorn Andersson" <andersson@...nel.org>, "Alim
Akhtar" <alim.akhtar@...sung.com>, "Avri Altman" <avri.altman@....com>,
"Bart Van Assche" <bvanassche@....org>, "Vinod Koul" <vkoul@...nel.org>,
"Konrad Dybcio" <konradybcio@...nel.org>
Cc: <~postmarketos/upstreaming@...ts.sr.ht>, <phone-devel@...r.kernel.org>,
<linux-arm-msm@...r.kernel.org>, <linux-crypto@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-scsi@...r.kernel.org>, <linux-phy@...ts.infradead.org>
Subject: Re: [PATCH 5/6] arm64: dts: qcom: milos: Add UFS nodes
Hi Neil,
On Mon Jan 12, 2026 at 9:26 AM CET, Neil Armstrong wrote:
> On 1/7/26 14:53, Neil Armstrong wrote:
>> Hi,
>>
>> On 1/7/26 09:05, Luca Weiss wrote:
>>> Add the nodes for the UFS PHY and UFS host controller, along with the
>>> ICE used for UFS.
>>>
>>> Signed-off-by: Luca Weiss <luca.weiss@...rphone.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/milos.dtsi | 127 +++++++++++++++++++++++++++++++++++-
>>> 1 file changed, 124 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
>>> index e1a51d43943f..0f69deabb60c 100644
>>> --- a/arch/arm64/boot/dts/qcom/milos.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/milos.dtsi
>>> @@ -797,9 +797,9 @@ gcc: clock-controller@...000 {
>>> <&sleep_clk>,
>>> <0>, /* pcie_0_pipe_clk */
>>> <0>, /* pcie_1_pipe_clk */
>>> - <0>, /* ufs_phy_rx_symbol_0_clk */
>>> - <0>, /* ufs_phy_rx_symbol_1_clk */
>>> - <0>, /* ufs_phy_tx_symbol_0_clk */
>>> + <&ufs_mem_phy 0>,
>>> + <&ufs_mem_phy 1>,
>>> + <&ufs_mem_phy 2>,
>>> <0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */
>>> #clock-cells = <1>;
>>> @@ -1151,6 +1151,127 @@ aggre2_noc: interconnect@...0000 {
>>> qcom,bcm-voters = <&apps_bcm_voter>;
>>> };
>>> + ufs_mem_phy: phy@...0000 {
>>> + compatible = "qcom,milos-qmp-ufs-phy";
>>> + reg = <0x0 0x01d80000 0x0 0x2000>;
>>> +
>>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>>> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>>> + <&tcsr TCSR_UFS_CLKREF_EN>;
>>> + clock-names = "ref",
>>> + "ref_aux",
>>> + "qref";
>>> +
>>> + resets = <&ufs_mem_hc 0>;
>>> + reset-names = "ufsphy";
>>> +
>>> + power-domains = <&gcc UFS_MEM_PHY_GDSC>;
>>> +
>>> + #clock-cells = <1>;
>>> + #phy-cells = <0>;
>>> +
>>> + status = "disabled";
>>> + };
>>> +
>>> + ufs_mem_hc: ufshc@...4000 {
>>> + compatible = "qcom,milos-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
>>> + reg = <0x0 0x01d84000 0x0 0x3000>;
>>> +
>>> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
>>> +
>>> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
>>> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
>>> + <&gcc GCC_UFS_PHY_AHB_CLK>,
>>> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
>>> + <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
>>> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
>>> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
>>> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
>>> + clock-names = "core_clk",
>>> + "bus_aggr_clk",
>>> + "iface_clk",
>>> + "core_clk_unipro",
>>> + "ref_clk",
>>> + "tx_lane0_sync_clk",
>>> + "rx_lane0_sync_clk",
>>> + "rx_lane1_sync_clk";
>>> +
>>> + resets = <&gcc GCC_UFS_PHY_BCR>;
>>> + reset-names = "rst";
>>> +
>>> + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
>>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
>>> + &cnoc_cfg SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
>>> + interconnect-names = "ufs-ddr",
>>> + "cpu-ufs";
>>> +
>>> + power-domains = <&gcc UFS_PHY_GDSC>;
>>> + required-opps = <&rpmhpd_opp_nom>;
>>> +
>>> + operating-points-v2 = <&ufs_opp_table>;
>>> +
>>> + iommus = <&apps_smmu 0x60 0>;
>>
>> dma-coherent ?
Given that downstream volcano.dtsi has dma-coherent in the ufshc@...4000
node, looks like this is missing in my patch.
>>
>> and no MCQ support ?
Not sure, I could only find one reference to MCQ on createpoint for
milos, but given there's no mcq_sqd/mcq_vs reg defined downstream, and I
couldn't find anything for the same register values in the .FLAT file, I
don't think Milos has MCQ? Feel free to prove me wrong though.
>
> So, people just ignore my comment ?
>
> Milos is based on SM8550, so it should have dma-coherent, for the MCQ
> I hope they used the fixed added to the SM8650 UFS controller for MCQ.
Not sure what this should mean regarding MCQ...
Regards
Luca
>
> Neil
>
>>
>> <snip>
>>
>> Thanks,
>> Neil
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