linux-kernel - Re: [PATCH v2] arm64: fix cleared E0POE bit after cpu

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Message-ID: <08af7447-1ea8-4513-907e-1902a661261f@arm.com>
Date: Mon, 12 Jan 2026 10:36:48 +0100
From: Kevin Brodsky <kevin.brodsky@....com>
To: Yeoreum Yun <yeoreum.yun@....com>
Cc: linux-pm@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-kernel@...r.kernel.org, rafael@...nel.org, pavel@...nel.org,
 catalin.marinas@....com, will@...nel.org, anshuman.khandual@....com,
 ryan.roberts@....com, yang@...amperecomputing.com, joey.gouly@....com,
 stable@...r.kernel.org
Subject: Re: [PATCH v2] arm64: fix cleared E0POE bit after
 cpu_suspend()/resume()

On 07/01/2026 18:30, Yeoreum Yun wrote:
> Hi Kevin,
>
> [...]
>
>>> @@ -144,6 +148,10 @@ SYM_FUNC_START(cpu_do_resume)
>>>  	msr	tcr_el1, x8
>>>  	msr	vbar_el1, x9
>>>  	msr	mdscr_el1, x10
>>> +alternative_if ARM64_HAS_TCR2
>>> +	ldr	x2, [x0, #104]
>>> +	msr	REG_TCR2_EL1, x2
>>> +alternative_else_nop_endif
>> Maybe this could be pushed further down cpu_do_resume, next to DISR_EL1
>> maybe (since it's also conditional)? Otherwise the diff LGTM:
> Sorry but IIUC, currently there is no DISR_EL1 save/restore not yet?

It's zeroed at the end of cpu_do_resume, but yes it's not saved.

> and I think current place is good where before restore SCTLR_EL1 which
> before MMU enabled.

Fair enough, and I can see that other registers are not restored in the
same order as they're saved, so we're not breaking an existing pattern.
Either way Catalin took the patch so this is settled :)

- Kevin