linux-kernel - Re: [PATCH v2] phy: fsl-imx8mq-usb: add debugfs to access control register

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Message-ID: <6j2yhzqt6x3k55vrqjrol2k2qrhqmobvwjedkujyet4loyajxa@vy55aajfuvxk>
Date: Mon, 12 Jan 2026 18:35:39 +0800
From: Xu Yang <xu.yang_2@....com>
To: Andrew Lunn <andrew@...n.ch>
Cc: vkoul@...nel.org, neil.armstrong@...aro.org, shawnguo@...nel.org, 
	kernel@...gutronix.de, festevam@...il.com, jun.li@....com, Frank.Li@....com, 
	linux-phy@...ts.infradead.org, imx@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] phy: fsl-imx8mq-usb: add debugfs to access control
 register

On Thu, Jan 08, 2026 at 03:47:17PM +0100, Andrew Lunn wrote:
> On Thu, Jan 08, 2026 at 04:22:24PM +0800, Xu Yang wrote:
> > On Wed, Dec 24, 2025 at 02:51:11PM +0100, Andrew Lunn wrote:
> > > On Wed, Dec 24, 2025 at 07:17:16PM +0800, Xu Yang wrote:
> > > > The CR port is a simple 16-bit data/address parallel port that is
> > > > provided for on-chip access to the control registers inside the
> > > > USB 3.0 femtoPHY. While access to these registers is not required
> > > > for normal PHY operation, this interface enables you to access
> > > > some of the PHY’s diagnostic features during normal operation or
> > > > to override some basic PHY control signals.
> > > > 
> > > > 3 debugfs files are created to read and write control registers,
> > > > all use hexadecimal format:
> > > > ctrl_reg_base: the register offset to write, or the start offset
> > > >                to read.
> > > > ctrl_reg_count: how many continuous registers to be read.
> > > > ctrl_reg_value: read to show the continuous registers value from
> > > >                 the offset in ctrl_reg_base, to ctrl_reg_base
> > > >                 + ctrl_reg_count - 1, one line for one register.
> > > >                 when write, override the register at ctrl_reg_base,
> > > >                 one time can only change one 16bits register.
> > > 
> > > Are the registers openly documented somewhere? Could you include a
> > > link in the commit message.
> > 
> > We integrate a SNPS PHY in Soc. So the registers are documented
> > in SNPS doc. Anyway, I can add a link for reference.
> 
> Humm, so the registers are defined by a Synopsys databook?
> 
> Shouldn't this patch be split into two? The access mechanism to the
> registers is specific to the imx8mq. But the registers themselves
> should be part of the generic SNPS PHY driver which should be shared
> by all devices using this licensed IP?

This patch mainly contain the access mechanism on i.MX Soc, so:
 - imx8mq_phy_ctrl_reg_addr()
 - imx8mq_phy_ctrl_reg_read()
 - imx8mq_phy_ctrl_reg_write()

and debugfs function to show them:
 - ctrl_reg_value_show()
 - ctrl_reg_value_write()

Do you mean split above into 2 patches? Put the first part into
phy-fsl-imx8mq-usb.c and the second part into a SNPS generic driver?

If so, do you know which generic driver should I use? If no such
driver, can I put them in phy-fsl-imx8mq-usb.c at the beginning?

Thanks,
Xu Yang