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Message-ID:
<MA5PR01MB1250095A65211598BF17058E5FE81A@MA5PR01MB12500.INDPRD01.PROD.OUTLOOK.COM>
Date: Mon, 12 Jan 2026 10:57:17 +0800
From: Chen Wang <unicorn_wang@...look.com>
To: Brian Masney <bmasney@...hat.com>,
Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>
Cc: linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
Inochi Amaoto <inochiama@...il.com>, sophgo@...ts.linux.dev
Subject: Re: [PATCH 17/27] clk: sophgo: sg2042-clkgen: convert from
divider_round_rate() to divider_determine_rate()
On 1/9/2026 5:16 AM, Brian Masney wrote:
> The divider_round_rate() function is now deprecated, so let's migrate
> to divider_determine_rate() instead so that this deprecated API can be
> removed.
>
> Note that when the main function itself was migrated to use
> determine_rate, this was mistakenly converted to:
>
> req->rate = divider_round_rate(...)
>
> This is invalid in the case when an error occurs since it can set the
> rate to a negative value.
>
> Note that this commit also removes a debugging message that's not really
> needed.
>
> Fixes: 9a3b6993613d ("clk: sophgo: sg2042-clkgen: convert from round_rate() to determine_rate()")
> Signed-off-by: Brian Masney <bmasney@...hat.com>
>
> ---
> To: Chen Wang <unicorn_wang@...look.com>
> To: Inochi Amaoto <inochiama@...il.com>
> Cc: sophgo@...ts.linux.dev
> ---
> drivers/clk/sophgo/clk-sg2042-clkgen.c | 15 +++++----------
> 1 file changed, 5 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/clk/sophgo/clk-sg2042-clkgen.c b/drivers/clk/sophgo/clk-sg2042-clkgen.c
> index 683661b71787c9e5428b168502f6fbb30ea9f7da..9725ac4e050a4e6afd3fd50241fbd2fc105a31ca 100644
> --- a/drivers/clk/sophgo/clk-sg2042-clkgen.c
> +++ b/drivers/clk/sophgo/clk-sg2042-clkgen.c
> @@ -180,7 +180,6 @@ static int sg2042_clk_divider_determine_rate(struct clk_hw *hw,
> struct clk_rate_request *req)
> {
> struct sg2042_divider_clock *divider = to_sg2042_clk_divider(hw);
> - unsigned long ret_rate;
> u32 bestdiv;
>
> /* if read only, just return current value */
> @@ -191,17 +190,13 @@ static int sg2042_clk_divider_determine_rate(struct clk_hw *hw,
> bestdiv = readl(divider->reg) >> divider->shift;
> bestdiv &= clk_div_mask(divider->width);
> }
> - ret_rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, bestdiv);
> - } else {
> - ret_rate = divider_round_rate(hw, req->rate, &req->best_parent_rate, NULL,
> - divider->width, divider->div_flags);
> - }
> + req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, bestdiv);
>
> - pr_debug("--> %s: divider_round_rate: val = %ld\n",
> - clk_hw_get_name(hw), ret_rate);
> - req->rate = ret_rate;
> + return 0;
> + }
>
> - return 0;
> + return divider_determine_rate(hw, req, NULL, divider->width,
> + divider->div_flags);
> }
>
> static int sg2042_clk_divider_set_rate(struct clk_hw *hw,
Tested-by: Chen Wang <unicorn_wang@...look.com>
Reviewed-by: Chen Wang <unicorn_wang@...look.com>
BTW: I have a question about the base-commit on which your patch series
is based. Could you please tell me where I can find this base-commit?
I'm asking this because I found that for the changes in [25/27]
phy-j721e-wiz, if I'm based on the latest upstream master, I can't
successfully apply this patch.
So, in my testing, I'm based on 6.19-rc1 and haven't picked [25/27].
Thanks,
Chen
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