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Message-Id: <20260113-v6-18-topic-clk-fracn-gppll-v1-2-166e674aabf1@pengutronix.de>
Date: Tue, 13 Jan 2026 13:29:07 +0100
From: Marco Felsch <m.felsch@...gutronix.de>
To: Abel Vesa <abelvesa@...nel.org>, Peng Fan <peng.fan@....com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>
Cc: linux-clk@...r.kernel.org, imx@...ts.linux.dev,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Marco Felsch <m.felsch@...gutronix.de>
Subject: [PATCH 2/2] clk: imx: fracn-gppll: Add 241.90 MHz Support
Some parallel panels have a pixelclk of 24.19 MHz. Add support for
241.90 MHz so a by 10 divider can be used to derive the exact pixelclk.
Signed-off-by: Marco Felsch <m.felsch@...gutronix.de>
---
drivers/clk/imx/clk-fracn-gppll.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
index 579f76494eb041dfba58b8cd10eb2453a0ec4178..eb3d5e3c53946f3caf83bcff654c6481611375e3 100644
--- a/drivers/clk/imx/clk-fracn-gppll.c
+++ b/drivers/clk/imx/clk-fracn-gppll.c
@@ -89,7 +89,8 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
PLL_FRACN_GP(332600000U, 138, 584, 1000, 0, 10),
- PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12)
+ PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12),
+ PLL_FRACN_GP(241900000U, 201, 584, 1000, 0, 20)
};
struct imx_fracn_gppll_clk imx_fracn_gppll = {
--
2.47.3
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