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Message-ID: <c08e5eeb-2949-4a13-951d-b7ae39d1e062@linux.intel.com>
Date: Tue, 13 Jan 2026 09:59:26 +0800
From: "Mi, Dapeng" <dapeng1.mi@...ux.intel.com>
To: Peter Zijlstra <peterz@...radead.org>
Cc: Ingo Molnar <mingo@...hat.com>, Arnaldo Carvalho de Melo
<acme@...nel.org>, Namhyung Kim <namhyung@...nel.org>,
Ian Rogers <irogers@...gle.com>, Adrian Hunter <adrian.hunter@...el.com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Andi Kleen <ak@...ux.intel.com>, Eranian Stephane <eranian@...gle.com>,
linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org,
Dapeng Mi <dapeng1.mi@...el.com>, Zide Chen <zide.chen@...el.com>,
Falcon Thomas <thomas.falcon@...el.com>, Xudong Hao <xudong.hao@...el.com>
Subject: Re: [Patch v2 3/7] perf/x86/intel: Add core PMU support for DMR
On 1/12/2026 6:41 PM, Peter Zijlstra wrote:
> On Mon, Jan 12, 2026 at 01:16:45PM +0800, Dapeng Mi wrote:
>> @@ -7906,6 +8072,22 @@ __init int intel_pmu_init(void)
>> intel_pmu_pebs_data_source_skl(true);
>> break;
>>
>> + case INTEL_DIAMONDRAPIDS_X:
>> + intel_pmu_init_pnc(NULL);
>> + x86_pmu.pebs_ept = 1;
>> + x86_pmu.hw_config = hsw_hw_config;
>> + x86_pmu.pebs_latency_data = pnc_latency_data;
>> + x86_pmu.get_event_constraints = glc_get_event_constraints;
>> + extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
>> + hsw_format_attr : nhm_format_attr;
>> + extra_skl_attr = skl_format_attr;
>> + mem_attr = glc_events_attrs;
>> + td_attr = glc_td_events_attrs;
>> + tsx_attr = glc_tsx_events_attrs;
>> + pr_cont("Panthercove events, ");
>> + name = "panthercove";
>> + break;
>> +
>> case INTEL_ALDERLAKE:
>> case INTEL_ALDERLAKE_L:
>> case INTEL_RAPTORLAKE:
> Does something like so make sense?
>
>
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -8066,6 +8066,9 @@ __init int intel_pmu_init(void)
>
> glc_common:
> intel_pmu_init_glc(NULL);
> + intel_pmu_pebs_data_source_skl(true);
> +
> + glc_base:
> x86_pmu.pebs_ept = 1;
> x86_pmu.hw_config = hsw_hw_config;
> x86_pmu.get_event_constraints = glc_get_event_constraints;
> @@ -8075,24 +8078,14 @@ __init int intel_pmu_init(void)
> mem_attr = glc_events_attrs;
> td_attr = glc_td_events_attrs;
> tsx_attr = glc_tsx_events_attrs;
> - intel_pmu_pebs_data_source_skl(true);
> break;
>
> case INTEL_DIAMONDRAPIDS_X:
> - intel_pmu_init_pnc(NULL);
> - x86_pmu.pebs_ept = 1;
> - x86_pmu.hw_config = hsw_hw_config;
> - x86_pmu.pebs_latency_data = pnc_latency_data;
> - x86_pmu.get_event_constraints = glc_get_event_constraints;
> - extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
> - hsw_format_attr : nhm_format_attr;
> - extra_skl_attr = skl_format_attr;
> - mem_attr = glc_events_attrs;
> - td_attr = glc_td_events_attrs;
> - tsx_attr = glc_tsx_events_attrs;
> pr_cont("Panthercove events, ");
> name = "panthercove";
> - break;
> + intel_pmu_init_pnc(NULL);
> + x86_pmu.pebs_latency_data = pnc_latency_data;
> + goto glc_base;
>
> case INTEL_ALDERLAKE:
> case INTEL_ALDERLAKE_L:
Yes, that looks better, but "goto behind" seems a little weird, I tweak the
code a little bit. Thanks.
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 77cf849a1381..85134d80d9fc 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -8155,26 +8155,23 @@ __init int intel_pmu_init(void)
x86_pmu.extra_regs = intel_rwc_extra_regs;
pr_cont("Granite Rapids events, ");
name = "granite_rapids";
+ goto glc_common;
+
+ case INTEL_DIAMONDRAPIDS_X:
+ intel_pmu_init_pnc(NULL);
+ x86_pmu.pebs_latency_data = pnc_latency_data;
+
+ pr_cont("Panthercove events, ");
+ name = "panthercove";
+ goto glc_base;
glc_common:
intel_pmu_init_glc(NULL);
- x86_pmu.pebs_ept = 1;
- x86_pmu.hw_config = hsw_hw_config;
- x86_pmu.get_event_constraints = glc_get_event_constraints;
- extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
- hsw_format_attr : nhm_format_attr;
- extra_skl_attr = skl_format_attr;
- mem_attr = glc_events_attrs;
- td_attr = glc_td_events_attrs;
- tsx_attr = glc_tsx_events_attrs;
intel_pmu_pebs_data_source_skl(true);
- break;
- case INTEL_DIAMONDRAPIDS_X:
- intel_pmu_init_pnc(NULL);
+ glc_base:
x86_pmu.pebs_ept = 1;
x86_pmu.hw_config = hsw_hw_config;
- x86_pmu.pebs_latency_data = pnc_latency_data;
x86_pmu.get_event_constraints = glc_get_event_constraints;
extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
hsw_format_attr : nhm_format_attr;
@@ -8182,8 +8179,6 @@ __init int intel_pmu_init(void)
mem_attr = glc_events_attrs;
td_attr = glc_td_events_attrs;
tsx_attr = glc_tsx_events_attrs;
- pr_cont("Panthercove events, ");
- name = "panthercove";
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