linux-kernel - [PATCH 2/2] dt-bindings: pinctrl: mcp23s08: Add multi-chip example

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Message-Id: <20260113-mcp23s17-multiple-addr-names-v1-2-f14b60f92c82@yoseli.org>
Date: Tue, 13 Jan 2026 15:29:48 +0100
From: Jean-Michel Hautbois via B4 Relay <devnull+jeanmichel.hautbois.yoseli.org@...nel.org>
To: Linus Walleij <linusw@...nel.org>, Rob Herring <robh@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, 
 Himanshu Bhavani <himanshu.bhavani@...iconsignals.io>
Cc: linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org, 
 devicetree@...r.kernel.org, 
 Jean-Michel Hautbois <jeanmichel.hautbois@...eli.org>
Subject: [PATCH 2/2] dt-bindings: pinctrl: mcp23s08: Add multi-chip example

From: Jean-Michel Hautbois <jeanmichel.hautbois@...eli.org>

Enable gpio-line-names property in the schema and add example showing
how to use it with multiple MCP23S08/17/18 chips sharing the same SPI
chip select. Names are assigned sequentially in hardware address order.

Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@...eli.org>
---
 .../bindings/pinctrl/microchip,mcp23s08.yaml       | 33 ++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml
index e07f4723de17..667be31b6da3 100644
--- a/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml
@@ -42,6 +42,8 @@ properties:
   interrupts:
     maxItems: 1
 
+  gpio-line-names: true
+
   reset-gpios:
     description: GPIO specifier for active-low reset pin.
     maxItems: 1
@@ -159,3 +161,34 @@ examples:
             microchip,spi-present-mask = /bits/ 8 <0x01>;
         };
     };
+
+  - |
+    /* Multiple chips sharing same SPI CS with gpio-line-names */
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        gpio@0 {
+            compatible = "microchip,mcp23s17";
+            reg = <0>;
+            gpio-controller;
+            #gpio-cells = <2>;
+            spi-max-frequency = <10000000>;
+            /* Two chips at hardware addresses 0 and 1 */
+            microchip,spi-present-mask = /bits/ 8 <0x03>;
+            /*
+             * Names assigned sequentially in address order.
+             * First 16 names for chip at address 0 (GPA0-7, GPB0-7).
+             * Next 16 names for chip at address 1 (GPA0-7, GPB0-7).
+             */
+            gpio-line-names =
+                "EXP0_GPA0", "EXP0_GPA1", "EXP0_GPA2", "EXP0_GPA3",
+                "EXP0_GPA4", "EXP0_GPA5", "EXP0_GPA6", "EXP0_GPA7",
+                "EXP0_GPB0", "EXP0_GPB1", "EXP0_GPB2", "EXP0_GPB3",
+                "EXP0_GPB4", "EXP0_GPB5", "EXP0_GPB6", "EXP0_GPB7",
+                "EXP1_GPA0", "EXP1_GPA1", "EXP1_GPA2", "EXP1_GPA3",
+                "EXP1_GPA4", "EXP1_GPA5", "EXP1_GPA6", "EXP1_GPA7",
+                "EXP1_GPB0", "EXP1_GPB1", "EXP1_GPB2", "EXP1_GPB3",
+                "EXP1_GPB4", "EXP1_GPB5", "EXP1_GPB6", "EXP1_GPB7";
+        };
+    };

-- 
2.39.5