linux-kernel - Re: [PATCH] PCI/sophgo: Avoid L0s and L1 on Sophgo 2044 PCIe Root Ports

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Message-Id: <176831590431.500768.9251307274356703200.b4-ty@kernel.org>
Date: Tue, 13 Jan 2026 20:21:44 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>
To: Lorenzo Pieralisi <lpieralisi@...nel.org>,
        Krzysztof Wilczyński <kwilczynski@...nel.org>,
        Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
        Chen Wang <unicorn_wang@...look.com>,
        Inochi Amaoto <inochiama@...il.com>
Cc: Han Gao <rabenda.cn@...il.com>, linux-pci@...r.kernel.org,
        sophgo@...ts.linux.dev, linux-kernel@...r.kernel.org,
        Yixun Lan <dlan@...too.org>, Longbin Li <looong.bin@...il.com>,
        Han Gao <gaohan@...as.ac.cn>
Subject: Re: [PATCH] PCI/sophgo: Avoid L0s and L1 on Sophgo 2044 PCIe Root
 Ports


On Fri, 09 Jan 2026 12:07:53 +0800, Inochi Amaoto wrote:
> Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> states for devicetree platforms") force enable ASPM on all device tree
> platform, the SG2044 root port breaks as it advertises L0s and L1
> capabilities without supporting it.
> 
> Mask the L0s and L1 Support advertised in Link Capabilities
> in the LINKCAP register SG2044 Root Ports, so the framework
> won't try to enable those states.
> 
> [...]

Applied, thanks!

[1/1] PCI/sophgo: Avoid L0s and L1 on Sophgo 2044 PCIe Root Ports
      commit: 613f3255a35a95f52575dd8c60b7ac9d711639ce

Best regards,
-- 
Manivannan Sadhasivam <mani@...nel.org>