Message-ID: <mlgfs2v4eoovrdjba5l72yceudut5fa3xvi57s6cxukyfkyau4@7oo3dfohn2z3>
Date: Tue, 13 Jan 2026 22:18:38 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Rob Herring <robh@...nel.org>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>, 
	Bjorn Helgaas <bhelgaas@...gle.com>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
	Conor Dooley <conor+dt@...nel.org>, Bartosz Golaszewski <brgl@...ev.pl>, 
	Damien Le Moal <dlemoal@...nel.org>, Niklas Cassel <cassel@...nel.org>, 
	Linus Walleij <linus.walleij@...aro.org>, Bartosz Golaszewski <brgl@...nel.org>, 
	linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-arm-msm@...r.kernel.org, Stephan Gerhold <stephan.gerhold@...aro.org>, 
	Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>, linux-pm@...r.kernel.org, linux-ide@...r.kernel.org, 
	Frank Li <Frank.Li@....com>
Subject: Re: [PATCH v5 2/5] dt-bindings: connector: Add PCIe M.2 Mechanical
 Key M connector

On Tue, Jan 13, 2026 at 10:37:33AM -0600, Rob Herring wrote:
> On Wed, Jan 07, 2026 at 07:41:24PM +0530, Manivannan Sadhasivam wrote:
> > Add the devicetree binding for PCIe M.2 Mechanical Key M connector defined
> > in the PCI Express M.2 Specification, r4.0, sec 5.3. This connector
> > provides interfaces like PCIe and SATA to attach the Solid State Drives
> > (SSDs) to the host machine along with additional interfaces like USB, and
> > SMBus for debugging and supplementary features.
> > 
> > The connector provides a primary power supply of 3.3v, along with an
> > optional 1.8v VIO supply for the Adapter I/O buffer circuitry operating at
> > 1.8v sideband signaling.
> > 
> > The connector also supplies optional signals in the form of GPIOs for fine
> > grained power management.
> > 
> > Reviewed-by: Frank Li <Frank.Li@....com>
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>
> > ---
> >  .../bindings/connector/pcie-m2-m-connector.yaml    | 133 +++++++++++++++++++++
> >  1 file changed, 133 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml b/Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml
> > new file mode 100644
> > index 000000000000..e912ee6f6a59
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml
> > @@ -0,0 +1,133 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/connector/pcie-m2-m-connector.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: PCIe M.2 Mechanical Key M Connector
> > +
> > +maintainers:
> > +  - Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>
> > +
> > +description:
> > +  A PCIe M.2 M connector node represents a physical PCIe M.2 Mechanical Key M
> > +  connector. The Mechanical Key M connectors are used to connect SSDs to the
> > +  host system over PCIe/SATA interfaces. These connectors also offer optional
> > +  interfaces like USB, SMBus.
> > +
> > +properties:
> > +  compatible:
> > +    const: pcie-m2-m-connector
> > +
> > +  vpcie3v3-supply:
> > +    description: A phandle to the regulator for 3.3v supply.
> > +
> > +  vpcie1v8-supply:
> > +    description: A phandle to the regulator for VIO 1.8v supply.
> > +
> > +  ports:
> > +    $ref: /schemas/graph.yaml#/properties/ports
> > +    description: OF graph bindings modeling the interfaces exposed on the
> > +      connector. Since a single connector can have multiple interfaces, every
> > +      interface has an assigned OF graph port number as described below.
> > +
> > +    properties:
> > +      port@0:
> > +        $ref: /schemas/graph.yaml#/properties/port
> > +        description: Host interfaces of the connector
> > +
> > +        properties:
> > +          endpoint@0:
> > +            $ref: /schemas/graph.yaml#/properties/endpoint
> > +            description: PCIe interface
> > +
> > +          endpoint@1:
> > +            $ref: /schemas/graph.yaml#/properties/endpoint
> > +            description: SATA interface
> > +
> > +        anyOf:
> > +          - required:
> > +              - endpoint@0
> > +          - required:
> > +              - endpoint@1
> > +
> > +      port@1:
> > +        $ref: /schemas/graph.yaml#/properties/port
> > +        description: USB 2.0 interface
> > +
> > +      i2c-parent:
> > +        $ref: /schemas/types.yaml#/definitions/phandle
> > +        description: SMBus interface
> 
> This belongs outside of 'ports'. I would expect you'd get an error if 
> you tried to put it here as '/schemas/graph.yaml#/properties/ports' 
> shouldn't allow it. Please include the property in the example.
> 

Okay.

> > +
> > +    required:
> > +      - port@0
> > +
> > +  clocks:
> > +    description: 32.768 KHz Suspend Clock (SUSCLK) input from the host system to
> > +      the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.1 for
> > +      more details.
> > +    maxItems: 1
> > +
> > +  pedet-gpios:
> > +    description: GPIO input to PEDET signal. This signal is used by the host
> > +      systems to determine the communication protocol that the M.2 card uses;
> > +      SATA signaling (low) or PCIe signaling (high). Refer, PCI Express M.2
> > +      Specification r4.0, sec 3.3.4.2 for more details.
> > +    maxItems: 1
> > +
> > +  viocfg-gpios:
> > +    description: GPIO output to IO voltage configuration (VIO_CFG) signal. This
> > +      signal is used by the M.2 card to indicate to the host system that the
> > +      card supports an independent IO voltage domain for the sideband signals.
> > +      Refer, PCI Express M.2 Specification r4.0, sec 3.1.15.1 for more details.
> > +    maxItems: 1
> > +
> > +  pwrdis-gpios:
> > +    description: GPIO input to Power Disable (PWRDIS) signal. This signal is
> > +      used by the host system to disable power on the M.2 card. Refer, PCI
> > +      Express M.2 Specification r4.0, sec 3.3.5.2 for more details.
> > +    maxItems: 1
> > +
> > +  pln-gpios:
> > +    description: GPIO output to Power Loss Notification (PLN#) signal. This
> > +      signal is use to notify the M.2 card by the host system that the power
> > +      loss event is expected to occur. Refer, PCI Express M.2 Specification
> > +      r4.0, sec 3.2.17.1 for more details.
> > +    maxItems: 1
> > +
> > +  plas3-gpios:
> > +    description: GPIO output to Power Loss Acknowledge (PLA_S3#) signal. This
> 
> GPIO input?
> 

I defined the role from a card PoV, but it should be the other way around, from
the connector/host PoV. In that case, this will become input. I will change
others also.

> > +      signal is used by the M.2 card to notify the host system, the status of
> > +      the M.2 card's preparation for power loss.
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - vpcie3v3-supply
> 
> All the GPIOs are really optional?
> 

Yes.

> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  # PCI M.2 Key M connector for SSDs with PCIe interface
> > +  - |
> > +    connector {
> > +        compatible = "pcie-m2-m-connector";
> > +        vpcie3v3-supply = <&vreg_nvme>;
> > +
> > +        ports {
> > +            #address-cells = <1>;
> > +            #size-cells = <0>;
> > +
> > +            port@0 {
> > +                #address-cells = <1>;
> > +                #size-cells = <0>;
> > +
> > +                reg = <0>;
> > +
> > +                endpoint@0 {
> > +                    reg = <0>;
> > +                    remote-endpoint = <&pcie6_port0_ep>;
> > +                };
> 
> Please make the example as complete as possible.
> 

Okay.

- Mani

-- 
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