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Message-ID: <20260113171522.3446407-1-haakon.bugge@oracle.com>
Date: Tue, 13 Jan 2026 18:15:20 +0100
From: Håkon Bugge <haakon.bugge@...cle.com>
To: "Rafael J. Wysocki" <rafael@...nel.org>, Len Brown <lenb@...nel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Greg Kroah-Hartman <gregkh@...e.de>,
Kenji Kaneshige <kaneshige.kenji@...fujitsu.com>
Cc: Håkon Bugge <haakon.bugge@...cle.com>,
linux-acpi@...r.kernel.org, linux-pci@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH] PCI/ACPI: Confine program_hpx_type2 to the AER bits
program_hpx_type2() is today unconditionally called, despite the fact
that when the _HPX was added to the ACPI spec. v3.0, the description
stated:
OSPM [1] will only evaluate _HPX with Setting Record – Type 2 if OSPM
is not controlling the PCI Express Advanced Error Reporting
capability.
Hence, we only call program_hpx_type2() when the OSPM owns the PCIe
hotplug capability but not the AER.
The Advanced Configuration and Power Interface (ACPI) Specification
version 6.6 has a provision that gives the OSPM the ability to control
the other PCIe Device Control bits any way. In a note in section
6.2.9, it is stated:
"OSPM may override the settings provided by the _HPX object's Type2
record (PCI Express Settings) or Type3 record (PCI Express Descriptor
Settings) when OSPM has assumed native control of the corresponding
feature."
So, in order to preserve the non-AER bits in PCIe Device Control, in
particular the performance sensitive ExtTag and RO, we make sure
program_hpx_type2() if called, doesn't modify any non-AER bits.
Also, when program_hpx_type2() is called, and any bits in the PCIe
Link Control register is set, we log a warning.
[1] Operating System-directed configuration and Power Management
Fixes: 40abb96c51bb ("[PATCH] pciehp: Fix programming hotplug parameters")
Signed-off-by: Håkon Bugge <haakon.bugge@...cle.com>
---
drivers/pci/pci-acpi.c | 71 ++++++++++++++++++++++--------------------
1 file changed, 37 insertions(+), 34 deletions(-)
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index 9369377725fa0..f36b51f6721a6 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -271,21 +271,6 @@ static acpi_status decode_type1_hpx_record(union acpi_object *record,
return AE_OK;
}
-static bool pcie_root_rcb_set(struct pci_dev *dev)
-{
- struct pci_dev *rp = pcie_find_root_port(dev);
- u16 lnkctl;
-
- if (!rp)
- return false;
-
- pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
- if (lnkctl & PCI_EXP_LNKCTL_RCB)
- return true;
-
- return false;
-}
-
/* _HPX PCI Express Setting Record (Type 2) */
struct hpx_type2 {
u32 revision;
@@ -311,6 +296,7 @@ static void program_hpx_type2(struct pci_dev *dev, struct hpx_type2 *hpx)
{
int pos;
u32 reg32;
+ const struct pci_host_bridge *host;
if (!hpx)
return;
@@ -318,40 +304,57 @@ static void program_hpx_type2(struct pci_dev *dev, struct hpx_type2 *hpx)
if (!pci_is_pcie(dev))
return;
+ host = pci_find_host_bridge(dev->bus);
+
+ /* We only do the HP programming if we own the PCIe native
+ * hotplug and not the AER ownership
+ */
+ if (!host->native_pcie_hotplug || host->native_aer)
+ return;
+
if (hpx->revision > 1) {
pci_warn(dev, "PCIe settings rev %d not supported\n",
hpx->revision);
return;
}
- /*
- * Don't allow _HPX to change MPS or MRRS settings. We manage
- * those to make sure they're consistent with the rest of the
+ /* We only allow _HPX to program the AER registers, namely
+ * PCI_EXP_DEVCTL_CERE, PCI_EXP_DEVCTL_NFERE,
+ * PCI_EXP_DEVCTL_FERE, and PCI_EXP_DEVCTL_URRE.
+ *
+ * The other settings in PCIe DEVCTL are managed by OS in
+ * order to make sure they're consistent with the rest of the
* platform.
*/
- hpx->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
- PCI_EXP_DEVCTL_READRQ;
- hpx->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
- PCI_EXP_DEVCTL_READRQ);
+ hpx->pci_exp_devctl_and |= PCI_EXP_DEVCTL_RELAX_EN |
+ PCI_EXP_DEVCTL_PAYLOAD |
+ PCI_EXP_DEVCTL_EXT_TAG |
+ PCI_EXP_DEVCTL_PHANTOM |
+ PCI_EXP_DEVCTL_AUX_PME |
+ PCI_EXP_DEVCTL_NOSNOOP_EN |
+ PCI_EXP_DEVCTL_READRQ |
+ PCI_EXP_DEVCTL_BCR_FLR;
+ hpx->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_RELAX_EN |
+ PCI_EXP_DEVCTL_PAYLOAD |
+ PCI_EXP_DEVCTL_EXT_TAG |
+ PCI_EXP_DEVCTL_PHANTOM |
+ PCI_EXP_DEVCTL_AUX_PME |
+ PCI_EXP_DEVCTL_NOSNOOP_EN |
+ PCI_EXP_DEVCTL_READRQ |
+ PCI_EXP_DEVCTL_BCR_FLR);
/* Initialize Device Control Register */
pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
~hpx->pci_exp_devctl_and, hpx->pci_exp_devctl_or);
- /* Initialize Link Control Register */
+ /* Log the Link Control Register if any bits are set */
if (pcie_cap_has_lnkctl(dev)) {
+ u16 lnkctl;
- /*
- * If the Root Port supports Read Completion Boundary of
- * 128, set RCB to 128. Otherwise, clear it.
- */
- hpx->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
- hpx->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
- if (pcie_root_rcb_set(dev))
- hpx->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
-
- pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
- ~hpx->pci_exp_lnkctl_and, hpx->pci_exp_lnkctl_or);
+ pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &lnkctl);
+ if (lnkctl)
+ pci_warn(dev, "Some bits in PCIe Link Control are set: 0x%04x\n",
+ lnkctl);
}
/* Find Advanced Error Reporting Enhanced Capability */
--
2.43.5
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