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Message-ID: <20260113182951.1059690-1-lukas.schmid@netcube.li>
Date: Tue, 13 Jan 2026 19:29:48 +0100
From: Lukas Schmid <lukas.schmid@...cube.li>
To: Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Chen-Yu Tsai <wens@...nel.org>,
Jernej Skrabec <jernej.skrabec@...il.com>,
Samuel Holland <samuel@...lland.org>,
Paul Walmsley <pjw@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>
Cc: linux-sunxi@...ts.linux.dev,
Alex Studer <alex@...der.dev>,
Lukas Schmid <lukas.schmid@...cube.li>,
devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org
Subject: [PATCH v2] riscv: dts: allwinner: d1: Add CPU thermal sensor and zone
From: Alex Studer <alex@...der.dev>
The sun20i THS (built in CPU thermal sensor) is supported in code, but
was never added to the device tree. So, add it to the device tree,
along with a thermal zone for the CPU.
Signed-off-by: Alex Studer <alex@...der.dev>
Link: https://lore.kernel.org/r/20250218020629.1476126-1-alex@studer.dev
Changes since v1:
- Move include before defines in sun20i-d1s.dtsi
- Fix register size for thermal-sensor@...9400
- Move thermal-sensor@...9400 in SoC to match register address sorting
- Add thermal-zone for sun8i-t113s.dtsi and fix missing cooling-cells
Signed-off-by: Lukas Schmid <lukas.schmid@...cube.li>
---
arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi | 33 +++++++++++++++++++
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 31 +++++++++++++++++
.../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 16 +++++++++
3 files changed, 80 insertions(+)
diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi
index c7181308ae6f..424f4a2487e2 100644
--- a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi
+++ b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi
@@ -4,6 +4,7 @@
#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
#include <riscv/allwinner/sunxi-d1s-t113.dtsi>
#include <riscv/allwinner/sunxi-d1-t113.dtsi>
@@ -20,6 +21,7 @@ cpu0: cpu@0 {
reg = <0>;
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -28,6 +30,7 @@ cpu1: cpu@1 {
reg = <1>;
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
+ #cooling-cells = <2>;
};
};
@@ -56,4 +59,34 @@ pmu {
<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
+
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths>;
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-crit {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
};
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
index a7442a508433..3f4ee820ef56 100644
--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
@@ -1,6 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2021-2022 Samuel Holland <samuel@...lland.org>
+#include <dt-bindings/thermal/thermal.h>
+
#define SOC_PERIPHERAL_IRQ(nr) (nr + 16)
#include "sunxi-d1s-t113.dtsi"
@@ -115,4 +117,33 @@ pmu {
<0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
};
+
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths>;
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-crit {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
};
diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
index 63e252b44973..ef7ebeab21ea 100644
--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
@@ -214,6 +214,18 @@ gpadc: adc@...9000 {
#io-channel-cells = <1>;
};
+ ths: thermal-sensor@...9400 {
+ compatible = "allwinner,sun20i-d1-ths";
+ reg = <0x2009400 0x400>;
+ interrupts = <SOC_PERIPHERAL_IRQ(58) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_THS>;
+ clock-names = "bus";
+ resets = <&ccu RST_BUS_THS>;
+ nvmem-cells = <&ths_calibration>;
+ nvmem-cell-names = "calibration";
+ #thermal-sensor-cells = <0>;
+ };
+
dmic: dmic@...1000 {
compatible = "allwinner,sun20i-d1-dmic",
"allwinner,sun50i-h6-dmic";
@@ -474,6 +486,10 @@ sid: efuse@...6000 {
reg = <0x3006000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ ths_calibration: thermal-sensor-calibration@14 {
+ reg = <0x14 0x8>;
+ };
};
crypto: crypto@...0000 {
--
2.47.3
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