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Message-ID: <20260113205651.GK812923@nvidia.com>
Date: Tue, 13 Jan 2026 16:56:51 -0400
From: Jason Gunthorpe <jgg@...dia.com>
To: Samiullah Khawaja <skhawaja@...gle.com>
Cc: Lu Baolu <baolu.lu@...ux.intel.com>, Joerg Roedel <joro@...tes.org>,
	Will Deacon <will@...nel.org>, Robin Murphy <robin.murphy@....com>,
	Kevin Tian <kevin.tian@...el.com>,
	Dmytro Maluka <dmaluka@...omium.org>, iommu@...ts.linux.dev,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/3] iommu/vt-d: Rework hitless PASID entry replacement

On Tue, Jan 13, 2026 at 11:27:30AM -0800, Samiullah Khawaja wrote:
> > - Update 'struct pasid_entry' with a union to support 128-bit
> >   access via the newly added val128[4] array.
> > - Add pasid_support_hitless_replace() to determine if a transition
> >   between an old and new entry is safe to perform atomically.
> >   - For First-level/Nested translations: The first 128 bits (chunk 0)
> >     must remain identical; chunk 1 is updated atomically.
> 
> Looking at the specs, the DID is part of the first 128 bits (chunk 0),
> so I guess for the first level the hitless replacement would not be
> supported since each domain will have a different DID?

Ah, yeah, you wont be able to do the KHO replace thing when using a
first stage..

Jason

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