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Message-ID: <aWa1vWN1c2oNPoZ1@x1>
Date: Tue, 13 Jan 2026 18:14:37 -0300
From: Arnaldo Carvalho de Melo <acme@...nel.org>
To: Ian Rogers <irogers@...gle.com>
Cc: Manuel Hernández | OPENCHIP <manuel.hernandez@...nchip.com>,
"acme@...hat.com" <acme@...hat.com>,
"adrian.hunter@...el.com" <adrian.hunter@...el.com>,
"alex@...ti.fr" <alex@...ti.fr>,
"alexander.shishkin@...ux.intel.com" <alexander.shishkin@...ux.intel.com>,
"aou@...s.berkeley.edu" <aou@...s.berkeley.edu>,
"eric.lin@...ive.com" <eric.lin@...ive.com>,
"inochiama@...il.com" <inochiama@...il.com>,
"jolsa@...nel.org" <jolsa@...nel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-perf-users@...r.kernel.org" <linux-perf-users@...r.kernel.org>,
"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
"mark.rutland@....com" <mark.rutland@....com>,
"mingo@...hat.com" <mingo@...hat.com>,
"namhyung@...nel.org" <namhyung@...nel.org>,
"palmer@...belt.com" <palmer@...belt.com>,
"peterz@...radead.org" <peterz@...radead.org>,
"pjw@...nel.org" <pjw@...nel.org>,
"samuel.holland@...ive.com" <samuel.holland@...ive.com>
Subject: Re: [PATCH v2] perf vendor events riscv: Add CVA6 JSON file
On Thu, Dec 04, 2025 at 08:43:51AM -0800, Ian Rogers wrote:
> On Thu, Dec 4, 2025 at 8:40 AM Manuel Hernández | OPENCHIP
> <manuel.hernandez@...nchip.com> wrote:
> >
> > From: Manuel Hernández Méndez <manuel.hernandez@...nchip.com>
> >
> > This patch add the CVA6 JSON file.
> >
> > Signed-off-by: Manuel Hernández Méndez <manuel.hernandez@...nchip.com>
>
> Reviewed-by: Ian Rogers <irogers@...gle.com>
Applied, and added a tad more info to the cset log message:
This patch add the OpenHW Core-V CVA6 Risc-V JSON file.
For more info:
https://openhwfoundation.org/news/2023/11/07/openhw-group-announces-core-v-cva6-platform-project-for-risc-v-software-development-and-testing/
:-)
- Arnaldo
> Thanks,
> Ian
>
> > ---
> > Hi Ian, thanks for the review.
> >
> > This is the second version of the patch, following a review of the
> > CVA6 core PMU implementation.
> >
> > Thanks!
> > Manuel
> > ---
> > Changes in v2:
> > - Added a clarification about retired instructions in name and
> > description fields
> > - Moved and renamed LOAD_ACCESSES and STORE_ACCESSES events from
> > memory.json to instructions.json
> > - Moved INSTRUCTION_FETCH_EMPTY event from instructions.json to
> > microarch.json
> > - Changed mode from 755 to 644 in firmware.json file
> >
> > v1:
> > https://lore.kernel.org/all/20251202180155.11147-1-manuel.hernandez@openchip.com/
> > ---
> > tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 +
> > .../arch/riscv/openhwgroup/cva6/firmware.json | 68 +++++++++++++++++++
> > .../riscv/openhwgroup/cva6/instructions.json | 47 +++++++++++++
> > .../arch/riscv/openhwgroup/cva6/memory.json | 42 ++++++++++++
> > .../riscv/openhwgroup/cva6/microarch.json | 27 ++++++++
> > 5 files changed, 185 insertions(+)
> > create mode 100644 tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/firmware.json
> > create mode 100644 tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/instructions.json
> > create mode 100644 tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/memory.json
> > create mode 100644 tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/microarch.json
> >
> > diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
> > index d5eea7f9aa9a..87cfb0e0849f 100644
> > --- a/tools/perf/pmu-events/arch/riscv/mapfile.csv
> > +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
> > @@ -21,5 +21,6 @@
> > 0x489-0x8000000000000[1-6]08-0x[9b][[:xdigit:]]+,v1,sifive/p650,core
> > 0x5b7-0x0-0x0,v1,thead/c900-legacy,core
> > 0x5b7-0x80000000090c0d00-0x2047000,v1,thead/c900-legacy,core
> > +0x602-0x3-0x0,v1,openhwgroup/cva6,core
> > 0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core
> > 0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core
> > diff --git a/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/firmware.json b/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/firmware.json
> > new file mode 100644
> > index 000000000000..7149caec4f80
> > --- /dev/null
> > +++ b/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/firmware.json
> > @@ -0,0 +1,68 @@
> > +[
> > + {
> > + "ArchStdEvent": "FW_MISALIGNED_LOAD"
> > + },
> > + {
> > + "ArchStdEvent": "FW_MISALIGNED_STORE"
> > + },
> > + {
> > + "ArchStdEvent": "FW_ACCESS_LOAD"
> > + },
> > + {
> > + "ArchStdEvent": "FW_ACCESS_STORE"
> > + },
> > + {
> > + "ArchStdEvent": "FW_ILLEGAL_INSN"
> > + },
> > + {
> > + "ArchStdEvent": "FW_SET_TIMER"
> > + },
> > + {
> > + "ArchStdEvent": "FW_IPI_SENT"
> > + },
> > + {
> > + "ArchStdEvent": "FW_IPI_RECEIVED"
> > + },
> > + {
> > + "ArchStdEvent": "FW_FENCE_I_SENT"
> > + },
> > + {
> > + "ArchStdEvent": "FW_FENCE_I_RECEIVED"
> > + },
> > + {
> > + "ArchStdEvent": "FW_SFENCE_VMA_SENT"
> > + },
> > + {
> > + "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
> > + },
> > + {
> > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT"
> > + },
> > + {
> > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
> > + },
> > + {
> > + "ArchStdEvent": "FW_HFENCE_GVMA_SENT"
> > + },
> > + {
> > + "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED"
> > + },
> > + {
> > + "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT"
> > + },
> > + {
> > + "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED"
> > + },
> > + {
> > + "ArchStdEvent": "FW_HFENCE_VVMA_SENT"
> > + },
> > + {
> > + "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED"
> > + },
> > + {
> > + "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT"
> > + },
> > + {
> > + "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED"
> > + }
> > +]
> > diff --git a/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/instructions.json b/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/instructions.json
> > new file mode 100644
> > index 000000000000..c38f6c97cf1f
> > --- /dev/null
> > +++ b/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/instructions.json
> > @@ -0,0 +1,47 @@
> > +[
> > + {
> > + "EventName": "LOAD_INSTRUCTIONS_RETIRED",
> > + "EventCode": "0x5",
> > + "BriefDescription": "number of data memory load instructions retired"
> > + },
> > + {
> > + "EventName": "STORE_INSTRUCTIONS_RETIRED",
> > + "EventCode": "0x6",
> > + "BriefDescription": "number of data memory store instructions retired"
> > + },
> > + {
> > + "EventName": "EXCEPTIONS",
> > + "EventCode": "0x7",
> > + "BriefDescription": "valid exceptions encountered"
> > + },
> > + {
> > + "EventName": "EXCEPTION_HANDLER_RETURNS",
> > + "EventCode": "0x8",
> > + "BriefDescription": "return from an exception"
> > + },
> > + {
> > + "EventName": "BRANCH_INSTRUCTIONS_RETIRED",
> > + "EventCode": "0x9",
> > + "BriefDescription": "number of branch instructions encountered retired"
> > + },
> > + {
> > + "EventName": "CALL_INSTRUCTIONS_RETIRED",
> > + "EventCode": "0xC",
> > + "BriefDescription": "number of call instructions retired"
> > + },
> > + {
> > + "EventName": "RETURN_INSTRUCTIONS_RETIRED",
> > + "EventCode": "0xD",
> > + "BriefDescription": "number of return instructions retired"
> > + },
> > + {
> > + "EventName": "INTEGER_INSTRUCTIONS_RETIRED",
> > + "EventCode": "0x14",
> > + "BriefDescription": "number of integer instructions retired"
> > + },
> > + {
> > + "EventName": "FLOATING_POINT_INSTRUCTIONS_RETIRED",
> > + "EventCode": "0x15",
> > + "BriefDescription": "number of floating point instructions retired"
> > + }
> > +]
> > diff --git a/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/memory.json b/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/memory.json
> > new file mode 100644
> > index 000000000000..c4f376a0ee4e
> > --- /dev/null
> > +++ b/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/memory.json
> > @@ -0,0 +1,42 @@
> > +[
> > + {
> > + "EventName": "L1_I_CACHE_MISSES",
> > + "EventCode": "0x1",
> > + "BriefDescription": "number of misses in L1 I-Cache"
> > + },
> > + {
> > + "EventName": "L1_D_CACHE_MISSES",
> > + "EventCode": "0x2",
> > + "BriefDescription": "number of misses in L1 D-Cache"
> > + },
> > + {
> > + "EventName": "ITLB_MISSES",
> > + "EventCode": "0x3",
> > + "BriefDescription": "number of misses in ITLB"
> > + },
> > + {
> > + "EventName": "DTLB_MISSES",
> > + "EventCode": "0x4",
> > + "BriefDescription": "number of misses in DTLB"
> > + },
> > + {
> > + "EventName": "L1_I_CACHE_ACCESSES",
> > + "EventCode": "0x10",
> > + "BriefDescription": "number of accesses to instruction cache"
> > + },
> > + {
> > + "EventName": "L1_D_CACHE_ACCESSES",
> > + "EventCode": "0x11",
> > + "BriefDescription": "number of accesses to data cache"
> > + },
> > + {
> > + "EventName": "L1_CACHE_LINE_EVICTION",
> > + "EventCode": "0x12",
> > + "BriefDescription": "number of data cache line eviction"
> > + },
> > + {
> > + "EventName": "ITLB_FLUSH",
> > + "EventCode": "0x13",
> > + "BriefDescription": "number of ITLB flushes"
> > + }
> > +]
> > diff --git a/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/microarch.json b/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/microarch.json
> > new file mode 100644
> > index 000000000000..104e6e8197da
> > --- /dev/null
> > +++ b/tools/perf/pmu-events/arch/riscv/openhwgroup/cva6/microarch.json
> > @@ -0,0 +1,27 @@
> > +[
> > + {
> > + "EventName": "BRANCH_MISPREDICTS",
> > + "EventCode": "0xA",
> > + "BriefDescription": "number of branch mispredictions"
> > + },
> > + {
> > + "EventName": "BRANCH_EXCEPTIONS",
> > + "EventCode": "0xB",
> > + "BriefDescription": "number of valid branch exceptions"
> > + },
> > + {
> > + "EventName": "MSB_FULL",
> > + "EventCode": "0xE",
> > + "BriefDescription": "scoreboard is full"
> > + },
> > + {
> > + "EventName": "INSTRUCTION_FETCH_EMPTY",
> > + "EventCode": "0xF",
> > + "BriefDescription": "number of invalid instructions in IF stage"
> > + },
> > + {
> > + "EventName": "PIPELINE_STALL",
> > + "EventCode": "0x16",
> > + "BriefDescription": "number of cycles the pipeline is stalled during read operands"
> > + }
> > +]
> > --
> > 2.34.1
> >
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