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Message-ID: <20260113220647.GA783058@bhelgaas>
Date: Tue, 13 Jan 2026 16:06:47 -0600
From: Bjorn Helgaas <helgaas@...nel.org>
To: liziyao@...ontech.com
Cc: Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof Wilczyński <kwilczynski@...nel.org>,
Manivannan Sadhasivam <mani@...nel.org>,
Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
niecheng1@...ontech.com, zhanjun@...ontech.com,
guanwentao@...ontech.com, Kexy Biscuit <kexybiscuit@...c.io>,
linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
loongarch@...ts.linux.dev,
Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>,
stable@...r.kernel.org, Lain Fearyncess Yang <fsf@...e.com>,
Ayden Meng <aydenmeng@...h.net>, Mingcong Bai <jeffbai@...c.io>,
Xi Ruoyao <xry111@...111.site>, Huacai Chen <chenhuacai@...nel.org>
Subject: Re: [PATCH v5] PCI: loongson: Override PCIe bridge supported speeds
for Loongson-3C6000 series
On Tue, Jan 13, 2026 at 03:58:48PM +0800, Ziyao Li via B4 Relay wrote:
> From: Ziyao Li <liziyao@...ontech.com>
>
> Older steppings of the Loongson-3C6000 series incorrectly report the
> supported link speeds on their PCIe bridges (device IDs 0x3c19, 0x3c29)
> as only 2.5 GT/s, despite the upstream bus supporting speeds from
> 2.5 GT/s up to 16 GT/s.
>
> As a result, since commit 774c71c52aa4 ("PCI/bwctrl: Enable only if more
> than one speed is supported"), bwctrl will be disabled if there's only
> one 2.5 GT/s value in vector `supported_speeds`.
>
> Also, amdgpu reads the value by pcie_get_speed_cap() in amdgpu_device_
> partner_bandwidth(), for its dynamic adjustment of PCIe clocks and
> lanes in power management. We hope this can prevent similar problems
> in future driver changes (similar checks may be implemented in other
> GPU, storage controller, NIC, etc. drivers).
Don't split amdgpu_device_partner_bandwidth() across lines; that makes
it hard to copy and grep for it.
Bjorn
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