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Message-ID: <176828328795.4027.16644210192638742005@lazor>
Date: Mon, 12 Jan 2026 22:48:07 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Brian Masney <bmasney@...hat.com>, Claudiu Beznea <claudiu.beznea@...on.dev>, Thomas Bogendoerfer <tsbogend@...ha.franken.de>
Cc: linux-mips@...r.kernel.org, linux-kernel@...r.kernel.org, Brian Masney <bmasney@...hat.com>, Michael Turquette <mturquette@...libre.com>, linux-clk@...r.kernel.org
Subject: Re: [PATCH v2 16/16] clk: microchip: core: allow driver to be compiled with COMPILE_TEST
Quoting Brian Masney (2026-01-12 15:48:10)
> diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig
> index 1b9e43eb54976b219a0277cc971f353fd6af226a..1e56a057319d97e20440fe4e107d26fa85c95ab1 100644
> --- a/drivers/clk/microchip/Kconfig
> +++ b/drivers/clk/microchip/Kconfig
> @@ -1,7 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0
>
> config COMMON_CLK_PIC32
> - def_bool COMMON_CLK && MACH_PIC32
> + def_bool (COMMON_CLK && MACH_PIC32) || COMPILE_TEST
>
> config MCHP_CLK_MPFS
> bool "Clk driver for PolarFire SoC"
> diff --git a/drivers/clk/microchip/clk-core.c b/drivers/clk/microchip/clk-core.c
> index 891bec5fe1bedea826ff9c3bd4099c90e2528ff9..ce3a24e061d145934c84843008efadc3b0e2cffa 100644
> --- a/drivers/clk/microchip/clk-core.c
> +++ b/drivers/clk/microchip/clk-core.c
> @@ -75,6 +75,7 @@
> /* SoC specific clock needed during SPLL clock rate switch */
> static struct clk_hw *pic32_sclk_hw;
>
> +#ifdef CONFIG_MATCH_PIC32
CONFIG_MACH_PIC32?
> /* add instruction pipeline delay while CPU clock is in-transition. */
> #define cpu_nop5() \
> do { \
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