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Message-ID: <773b6e43-4f86-4b11-8e6b-a9f2561a75de@nxp.com>
Date: Tue, 13 Jan 2026 14:41:07 +0800
From: Joseph Guo <qijian.guo@....com>
To: Marek Vasut <marek.vasut+renesas@...lbox.org>,
dri-devel@...ts.freedesktop.org
Cc: Andrzej Hajda <andrzej.hajda@...el.com>,
Conor Dooley <conor+dt@...nel.org>, David Airlie <airlied@...il.com>,
Jernej Skrabec <jernej.skrabec@...il.com>, Jonas Karlman <jonas@...boo.se>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Neil Armstrong <neil.armstrong@...aro.org>, Rob Herring <robh@...nel.org>,
Robert Foss <rfoss@...nel.org>, Simona Vetter <simona@...ll.ch>,
Thomas Zimmermann <tzimmermann@...e.de>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org
Subject: Re: [EXT] [PATCH 2/2] drm/bridge: waveshare-dsi: Add support for 1..4
DSI data lanes
On 1/13/2026 7:47 AM, Marek Vasut wrote:
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> Parse the data lane count out of DT. Limit the supported data lanes
> to 1..4 which is the maximum available DSI pairs on the connector of
> any known panels which may use this bridge. Internally, this bridge
> is an ChipOne ICN6211 which loads its register configuration from a
> dedicated storage and its I2C does not seem to be accessible. The
> ICN6211 also supports up to 4 DSI lanes, so this is a hard limit.
>
> To avoid any breakage on old DTs where the parsing of data lanes from
> DT may fail, fall back to the original hard-coded value of 2 lanes and
> warn user.
>
> The lane configuration is preconfigured in the bridge for each of the
> WaveShare panels. The 13.3" DSI panel works with 4-lane configuration,
> others seem to use 2-lane configuration. This is a hardware property,
> so the actual count should come from DT.
>
>
Hi Marek,
I don't have 4 lanes waveshare panel on my hands. Have you tested with the 4-lane panel already?
Regards,
Joseph
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