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Message-ID: <u3d62zn56yj6k56t4jwcqylm4rofipp2f42dgpi2kqgumowzu7@m5iqfem5y5up>
Date: Tue, 13 Jan 2026 12:43:11 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Sivareddy Surasani <sivareddy.surasani@....qualcomm.com>
Cc: Jonathan Corbet <corbet@....net>, Arnd Bergmann <arnd@...db.de>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>, mhi@...ts.linux.dev, linux-arm-msm@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org,
Upal Kumar Saha <upal.saha@....qualcomm.com>, Himanshu Shukla <quic_himashuk@...cinc.com>,
Vivek Pernamitta <vivek.pernamitta@....qualcomm.com>, Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
Subject: Re: [PATCH 01/11] bus: mhi: host: Add support to read MHI
capabilities
On Thu, Dec 11, 2025 at 01:37:33PM +0530, Sivareddy Surasani wrote:
> From: Vivek Pernamitta <vivek.pernamitta@....qualcomm.com>
>
> As per MHI spec v1.2,sec 6.6, MHI has capability registers which are
> located after the ERDB array. The location of this group of registers is
> indicated by the MISCOFF register. Each capability has a capability ID to
> determine which functionality is supported and each capability will point
> to the next capability supported.
>
> Add a basic function to read those capabilities offsets.
>
> Signed-off-by: Vivek Pernamitta <vivek.pernamitta@....qualcomm.com>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
> Signed-off-by: Sivareddy Surasani <sivareddy.surasani@....qualcomm.com>
> ---
> drivers/bus/mhi/common.h | 13 +++++++++++++
> drivers/bus/mhi/host/init.c | 32 ++++++++++++++++++++++++++++++++
> 2 files changed, 45 insertions(+)
>
> diff --git a/drivers/bus/mhi/common.h b/drivers/bus/mhi/common.h
> index dda340aaed95..58f27c6ba63e 100644
> --- a/drivers/bus/mhi/common.h
> +++ b/drivers/bus/mhi/common.h
> @@ -16,6 +16,7 @@
> #define MHICFG 0x10
> #define CHDBOFF 0x18
> #define ERDBOFF 0x20
> +#define MISCOFF 0x24
> #define BHIOFF 0x28
> #define BHIEOFF 0x2c
> #define DEBUGOFF 0x30
> @@ -113,6 +114,9 @@
> #define MHISTATUS_MHISTATE_MASK GENMASK(15, 8)
> #define MHISTATUS_SYSERR_MASK BIT(2)
> #define MHISTATUS_READY_MASK BIT(0)
> +#define MISC_CAP_MASK GENMASK(31, 0)
> +#define CAP_CAPID_MASK GENMASK(31, 24)
> +#define CAP_NEXT_CAP_MASK GENMASK(23, 12)
>
> /* Command Ring Element macros */
> /* No operation command */
> @@ -204,6 +208,15 @@
> #define MHI_RSCTRE_DATA_DWORD1 cpu_to_le32(FIELD_PREP(GENMASK(23, 16), \
> MHI_PKT_TYPE_COALESCING))
>
> +enum mhi_capability_type {
> + MHI_CAP_ID_INTX = 0x1,
> + MHI_CAP_ID_TIME_SYNC = 0x2,
> + MHI_CAP_ID_BW_SCALE = 0x3,
> + MHI_CAP_ID_TSC_TIME_SYNC = 0x4,
> + MHI_CAP_ID_MAX_TRB_LEN = 0x5,
> + MHI_CAP_ID_MAX,
> +};
If you are not going to define a variable with type 'mhi_capability_type', I'd
suggest using '#define'.
> +
> enum mhi_pkt_type {
> MHI_PKT_TYPE_INVALID = 0x0,
> MHI_PKT_TYPE_NOOP_CMD = 0x1,
> diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c
> index 099be8dd1900..4c092490c9fd 100644
> --- a/drivers/bus/mhi/host/init.c
> +++ b/drivers/bus/mhi/host/init.c
> @@ -466,6 +466,38 @@ static int mhi_init_dev_ctxt(struct mhi_controller *mhi_cntrl)
> return ret;
> }
>
> +static int mhi_find_capability(struct mhi_controller *mhi_cntrl, u32 capability, u32 *offset)
> +{
Why can't you return the cap offset like pci_find_capability()?
- Mani
--
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