lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <ghggubfqnfdncjh32artxhznim5sdo7kanw4beu54m55koz47l@eg4o3njh5eii>
Date: Tue, 13 Jan 2026 13:35:47 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Sivareddy Surasani <sivareddy.surasani@....qualcomm.com>
Cc: Jonathan Corbet <corbet@....net>, Arnd Bergmann <arnd@...db.de>, 
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>, mhi@...ts.linux.dev, linux-arm-msm@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org, 
	Upal Kumar Saha <upal.saha@....qualcomm.com>, Himanshu Shukla <quic_himashuk@...cinc.com>, 
	Vivek Pernamitta <vivek.pernamitta@....qualcomm.com>
Subject: Re: [PATCH 06/11] bus: mhi: host: pci: Add overflow disable flag for
 QDU100 H/W channels

On Thu, Dec 11, 2025 at 01:37:38PM +0530, Sivareddy Surasani wrote:
> From: Vivek Pernamitta <vivek.pernamitta@....qualcomm.com>
> 
> Add overflow disable flag for QDU100 H/W channels.
> 

Add some context on why the channel require this flag and how it is used.

- Mani

> Signed-off-by: Vivek Pernamitta <vivek.pernamitta@....qualcomm.com>
> Signed-off-by: Sivareddy Surasani <sivareddy.surasani@....qualcomm.com>
> ---
>  drivers/bus/mhi/host/pci_generic.c | 20 ++++++++++++++++++--
>  1 file changed, 18 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c
> index bb3c5350a462..814f8fdae378 100644
> --- a/drivers/bus/mhi/host/pci_generic.c
> +++ b/drivers/bus/mhi/host/pci_generic.c
> @@ -94,6 +94,22 @@ struct mhi_pci_dev_info {
>  		.doorbell_mode_switch = false,		\
>  	}
>  
> +#define MHI_CHANNEL_CONFIG_DL_OVF_DISABLE(ch_num, ch_name, el_count, ev_ring) \
> +	{						\
> +		.num = ch_num,				\
> +		.name = ch_name,			\
> +		.num_elements = el_count,		\
> +		.event_ring = ev_ring,			\
> +		.dir = DMA_FROM_DEVICE,			\
> +		.ee_mask = BIT(MHI_EE_AMSS),		\
> +		.pollcfg = 0,				\
> +		.ovf_disable = true,			\
> +		.doorbell = MHI_DB_BRST_DISABLE,	\
> +		.lpm_notify = false,			\
> +		.offload_channel = false,		\
> +		.doorbell_mode_switch = false,		\
> +	}
> +
>  #define MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(ch_num, ch_name, el_count, ev_ring) \
>  	{						\
>  		.num = ch_num,				\
> @@ -295,9 +311,9 @@ static const struct mhi_channel_config mhi_qcom_qdu100_channels[] = {
>  static const struct mhi_channel_config mhi_qcom_qdu100_vf_channels[] = {
>  	/* HW channels */
>  	MHI_CHANNEL_CONFIG_UL(104, "IP_HW1", 2048, 1),
> -	MHI_CHANNEL_CONFIG_DL(105, "IP_HW1", 2048, 2),
> +	MHI_CHANNEL_CONFIG_DL_OVF_DISABLE(105, "IP_HW1", 2048, 2),
>  	MHI_CHANNEL_CONFIG_UL(106, "IP_HW2", 2048, 3),
> -	MHI_CHANNEL_CONFIG_DL(107, "IP_HW2", 2048, 4),
> +	MHI_CHANNEL_CONFIG_DL_OVF_DISABLE(107, "IP_HW2", 2048, 4),
>  };
>  
>  static struct mhi_event_config mhi_qcom_qdu100_events[] = {
> 
> -- 
> 2.34.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ