linux-kernel - Re: [PATCH] arm64: dts: qcom: sm8750: Enable download mode register write

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Message-ID: <cca646c3-5e74-47cf-9dfa-49a888db0414@oss.qualcomm.com>
Date: Tue, 13 Jan 2026 10:20:58 +0100
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Mukesh Ojha <mukesh.ojha@....qualcomm.com>, andersson@...nel.org,
        konradybcio@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
        conor+dt@...nel.org
Cc: devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: qcom: sm8750: Enable download mode register
 write

On 1/13/26 10:16 AM, Konrad Dybcio wrote:
> On 1/12/26 4:17 PM, Mukesh Ojha wrote:
>> Enable download mode setting for sm8750 which can help collect
>> ramdump for this SoC.
>>
>> Signed-off-by: Mukesh Ojha <mukesh.ojha@....qualcomm.com>
>> ---
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>

Actually no, we have a mess to undo..

There's already this node:

tcsrcc: clock-controller@...4008 {
        compatible = "qcom,sm8750-tcsr", "syscon";
        reg = <0x0 0x0f204008 0x0 0x3004>;

        clocks = <&rpmhcc RPMH_CXO_CLK>;

        #clock-cells = <1>;
        #reset-cells = <1>;
};

That's located at the rear end of TLMM (someone had a funny idea to
move registers around when designing this specific SoC)

Problem is, those registers aren't actually "TCSRCC", not even "TCSR"
Physically, they belong to the TLMM register window (which starts at
the base it promises under the TLMM node today and is 0xf0_0000-long.

What we should have done for a fairer representation is make TLMM a
clock provider on this specific platform

qcom,sm8750-tcsr binds the tcsrcc driver, so we can't describe the
actual TCSR (as in this patch).. we'll have to break something..

Konrad