linux-kernel - [PATCH] arm64: dts: amlogic: S4: fix SD card initialization failure

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Message-Id: <20260113011931.40424-1-nick@khadas.com>
Date: Tue, 13 Jan 2026 09:19:31 +0800
From: Nick Xie <xieqinick@...il.com>
To: neil.armstrong@...aro.org,
	khilman@...libre.com,
	jbrunet@...libre.com,
	martin.blumenstingl@...glemail.com,
	xianwei.zhao@...ogic.com,
	devicetree@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-amlogic@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Cc: krzk+dt@...nel.org,
	conor+dt@...nel.org,
	robh@...nel.org,
	nick@...das.com
Subject: [PATCH] arm64: dts: amlogic: S4: fix SD card initialization failure

The SD controller (sd@...8a000) requires a clock source capable of
generating a 400kHz frequency for the identification phase.

Currently, the sd node uses CLKID_SD_EMMC_B as clkin0 and CLKID_FCLK_DIV2
as clkin1. Both of these are high-frequency clocks (e.g., ~1GHz).
The internal divider of the SD controller is limited to a maximum value
of 64 (2^6). With input frequencies significantly higher than 25.6MHz
(400kHz * 64), the driver is unable to generate the required 400kHz
clock, causing the probe to fail with -EINVAL.

Fix this by reparenting clkin0 to the 24MHz XTAL clock, consistent with
the configuration of the sdio and emmc nodes. This allows the divider
to successfully generate 400kHz (24MHz / 60).

Verified on Khadas VIM1S with SoC S4 S905Y4.

Fixes: 3ab9d54b5d847 ("arm64: dts: amlogic: enable some device nodes for S4")

Signed-off-by: Nick Xie <nick@...das.com>
---
 arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
index 9d99ed2994dfa..b87bc83b5a9bb 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
@@ -833,7 +833,7 @@ sd: mmc@...8a000 {
 			reg = <0x0 0xfe08a000 0x0 0x800>;
 			interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
 			clocks = <&clkc_periphs CLKID_SDEMMC_B>,
-				 <&clkc_periphs CLKID_SD_EMMC_B>,
+				 <&xtal>,
 				 <&clkc_pll CLKID_FCLK_DIV2>;
 			clock-names = "core", "clkin0", "clkin1";
 			resets = <&reset RESET_SD_EMMC_B>;
-- 
2.34.1