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Message-ID: <176935356287.13018.17884535923723366958.b4-ty@gentoo.org>
Date: Wed, 14 Jan 2026 09:41:12 +0800
From: Yixun Lan <dlan@...too.org>
To: Stephen Boyd <sboyd@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: Yixun Lan <dlan@...too.org>,
Haylen Chu <heylenay@....org>,
Guodong Xu <guodong@...cstar.com>,
Inochi Amaoto <inochiama@...il.com>,
Yao Zi <me@...ao.cc>,
linux-clk@...r.kernel.org,
devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org,
spacemit@...ts.linux.dev,
linux-kernel@...r.kernel.org,
Krzysztof Kozlowski <krzysztof.kozlowski@....qualcomm.com>
Subject: Re: [PATCH v5 0/5] Add clock support for SpacemiT K3 SoC
On 10:11 Thu 08 Jan , Yixun Lan wrote:
> I've dropped the RFC tag as now the driver got tested on K3 SoC.
>
> The SpacemiT K3 SoC's CCU (clock control unit) is similar to old K1 generation,
> the clock and reset functionalities are distributed across several IP blocks,
> therefore, we model them as several clock tree accordingly.
>
> The PLL clocks has changed register setting layout, so introduce a PLLA type.
> Some gate clocks has inverted enable/disable logic which writing 1 to disable,
> while writing 0 to enable.
>
> [...]
Applied, thanks!
[1/5] dt-bindings: soc: spacemit: k3: add clock support
https://github.com/spacemit-com/linux/commit/efe897b557e211a09f51d749eae5eca933e8bf56
[2/5] clk: spacemit: ccu_mix: add inverted enable gate clock
https://github.com/spacemit-com/linux/commit/ace73b7e27633ec770cfb24cd4ff42c24815a9aa
[3/5] clk: spacemit: ccu_pll: add plla type clock
https://github.com/spacemit-com/linux/commit/3a086236c600739d6653c0405d86aff7d6f03c06
[4/5] clk: spacemit: k3: extract common header
https://github.com/spacemit-com/linux/commit/091d19cc24018f2bd783e932fb2403cb7a2bdb3c
[5/5] clk: spacemit: k3: add the clock tree
https://github.com/spacemit-com/linux/commit/e371a77255b837f5d64c9d2520f87e41ea5350b9
Best regards,
--
Yixun Lan <dlan@...too.org>
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