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Message-Id: <20260114-acpm-tmu-v1-7-cfe56d93e90f@linaro.org>
Date: Wed, 14 Jan 2026 14:16:35 +0000
From: Tudor Ambarus <tudor.ambarus@...aro.org>
To: "Rafael J. Wysocki" <rafael@...nel.org>,
Daniel Lezcano <daniel.lezcano@...aro.org>, Zhang Rui <rui.zhang@...el.com>,
Lukasz Luba <lukasz.luba@....com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Lee Jones <lee@...nel.org>,
Krzysztof Kozlowski <krzk@...nel.org>,
Alim Akhtar <alim.akhtar@...sung.com>,
Peter Griffin <peter.griffin@...aro.org>,
André Draszik <andre.draszik@...aro.org>,
Bartlomiej Zolnierkiewicz <bzolnier@...il.com>, Kees Cook <kees@...nel.org>,
"Gustavo A. R. Silva" <gustavoars@...nel.org>
Cc: willmcvicker@...gle.com, jyescas@...gle.com, shin.son@...sung.com,
linux-pm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org, linux-hardening@...r.kernel.org,
Tudor Ambarus <tudor.ambarus@...aro.org>
Subject: [PATCH 7/8] arm64: dts: exynos: gs101: Add thermal management unit
Add the Thermal Management Unit (TMU) nodes for the Google GS101 SoC.
This includes:
- The top-level TMU sensor node linked to the ACPM block.
- The TMU syscon node for direct interrupt register access.
- Thermal zones for the CPU clusters (little, mid, big) with associated
trip points and cooling maps.
This enables thermal monitoring and mitigation on GS101 based devices.
Signed-off-by: Tudor Ambarus <tudor.ambarus@...aro.org>
---
arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi | 209 +++++++++++++++++++++++
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 22 +++
2 files changed, 231 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi b/arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..6262c3b890aa2f7ad572c32b30bf926df804ec1e
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi
@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Google GS101 TMU configurations device tree source
+ *
+ * Copyright 2020 Samsung Electronics Co., Ltd.
+ * Copyright 2020 Google LLC.
+ * Copyright 2026 Linaro Ltd.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ thermal-zones {
+ cpucl2-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tmu_top 0>;
+
+ trips {
+ big_cold: big-cold {
+ temperature = <20000>;
+ hysteresis = <5000>;
+ type = "active";
+ };
+
+ big_switch_on: big-switch-on {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ big_control_temp: big-control-temp {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ big_pre_switch_on: big-pre-switch-on {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ big_alert2: big-alert2 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "active";
+ };
+
+ big_hw_throttling: big-hw-throttling {
+ temperature = <103000>;
+ hysteresis = <5000>;
+ type = "active";
+ };
+
+ big_pause: big-pause {
+ temperature = <108000>;
+ hysteresis = <5000>;
+ type = "active";
+ };
+
+ big_hot: big-hot {
+ temperature = <115000>;
+ hysteresis = <3000>;
+ type = "hot";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&big_control_temp>;
+ cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpucl1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tmu_top 1>;
+
+ trips {
+ mid_cold: mid-cold {
+ temperature = <20000>;
+ hysteresis = <5000>;
+ type = "active";
+ };
+
+ mid_switch_on: mid-switch-on {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ mid_control_temp: mid-control-temp {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ mid_pre_switch_on: mid-pre-switch-on {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ mid_alert2: mid-alert2 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "active";
+ };
+
+ mid_hw_throttling: mid-hw-throttling {
+ temperature = <98000>;
+ hysteresis = <5000>;
+ type = "active";
+ };
+
+ mid_pause: mid-pause {
+ temperature = <108000>;
+ hysteresis = <5000>;
+ type = "active";
+ };
+
+ mid_hot: mid-hot {
+ temperature = <115000>;
+ hysteresis = <3000>;
+ type = "hot";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&mid_control_temp>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpucl0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tmu_top 2>;
+
+ trips {
+ little_cold: little-cold {
+ temperature = <20000>;
+ hysteresis = <5000>;
+ type = "active";
+ };
+
+ little_switch_on: little-switch-on {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ little_control_temp: little-control-temp {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ little_pre_switch_on: little-pre-switch-on {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ little_alert2: little-alert2 {
+ temperature = <100000>;
+ hysteresis = <5000>;
+ type = "active";
+ };
+
+ little_alert5: little-alert5 {
+ temperature = <103000>;
+ hysteresis = <5000>;
+ type = "active";
+ };
+
+ little_alert6: little-alert6 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "active";
+ };
+
+ little_hot: little-hot {
+ temperature = <115000>;
+ hysteresis = <3000>;
+ type = "hot";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&little_control_temp>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ };
+};
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index 48f3819590cf8c05d6bd7241cfed8720149c7db4..a2d5ed832588b83ec47e8c6833073c9ec95f2517 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -74,6 +74,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0x0000>;
clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>;
+ #cooling-cells = <2>;
enable-method = "psci";
cpu-idle-states = <&ananke_cpu_sleep>;
capacity-dmips-mhz = <250>;
@@ -86,6 +87,7 @@ cpu1: cpu@100 {
compatible = "arm,cortex-a55";
reg = <0x0100>;
clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>;
+ #cooling-cells = <2>;
enable-method = "psci";
cpu-idle-states = <&ananke_cpu_sleep>;
capacity-dmips-mhz = <250>;
@@ -98,6 +100,7 @@ cpu2: cpu@200 {
compatible = "arm,cortex-a55";
reg = <0x0200>;
clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>;
+ #cooling-cells = <2>;
enable-method = "psci";
cpu-idle-states = <&ananke_cpu_sleep>;
capacity-dmips-mhz = <250>;
@@ -110,6 +113,7 @@ cpu3: cpu@300 {
compatible = "arm,cortex-a55";
reg = <0x0300>;
clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>;
+ #cooling-cells = <2>;
enable-method = "psci";
cpu-idle-states = <&ananke_cpu_sleep>;
capacity-dmips-mhz = <250>;
@@ -122,6 +126,7 @@ cpu4: cpu@400 {
compatible = "arm,cortex-a76";
reg = <0x0400>;
clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>;
+ #cooling-cells = <2>;
enable-method = "psci";
cpu-idle-states = <&enyo_cpu_sleep>;
capacity-dmips-mhz = <620>;
@@ -134,6 +139,7 @@ cpu5: cpu@500 {
compatible = "arm,cortex-a76";
reg = <0x0500>;
clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>;
+ #cooling-cells = <2>;
enable-method = "psci";
cpu-idle-states = <&enyo_cpu_sleep>;
capacity-dmips-mhz = <620>;
@@ -146,6 +152,7 @@ cpu6: cpu@600 {
compatible = "arm,cortex-x1";
reg = <0x0600>;
clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>;
+ #cooling-cells = <2>;
enable-method = "psci";
cpu-idle-states = <&hera_cpu_sleep>;
capacity-dmips-mhz = <1024>;
@@ -158,6 +165,7 @@ cpu7: cpu@700 {
compatible = "arm,cortex-x1";
reg = <0x0700>;
clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>;
+ #cooling-cells = <2>;
enable-method = "psci";
cpu-idle-states = <&hera_cpu_sleep>;
capacity-dmips-mhz = <1024>;
@@ -489,6 +497,14 @@ acpm_ipc: power-management {
#clock-cells = <1>;
mboxes = <&ap2apm_mailbox>;
shmem = <&apm_sram>;
+
+ tmu_top: thermal-sensor {
+ compatible = "google,gs101-tmu-top";
+ clocks = <&cmu_misc CLK_GOUT_MISC_TMU_TOP_PCLK>;
+ interrupts = <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH 0>;
+ syscon = <&tmu_top_syscon>;
+ #thermal-sensor-cells = <1>;
+ };
};
};
@@ -639,6 +655,11 @@ watchdog_cl1: watchdog@...70000 {
status = "disabled";
};
+ tmu_top_syscon: syscon@...a0000 {
+ compatible = "google,gs101-tmu-syscon", "syscon";
+ reg = <0x100a0000 0x800>;
+ };
+
trng: rng@...41400 {
compatible = "google,gs101-trng",
"samsung,exynos850-trng";
@@ -1844,3 +1865,4 @@ timer {
};
#include "gs101-pinctrl.dtsi"
+#include "gs101-tmu.dtsi"
--
2.52.0.457.g6b5491de43-goog
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