linux-kernel - Re: [PATCH V8 3/4] dt-bindings: iommu: Add NVIDIA Tegra CMDQV support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <3bdfd531-698c-40a7-be76-254c122dfcb6@nvidia.com>
Date: Wed, 14 Jan 2026 15:23:49 +0000
From: Jon Hunter <jonathanh@...dia.com>
To: Ashish Mhetre <amhetre@...dia.com>, will@...nel.org,
 robin.murphy@....com, joro@...tes.org, robh@...nel.org, krzk+dt@...nel.org,
 conor+dt@...nel.org, nicolinc@...dia.com
Cc: thierry.reding@...il.com, vdumpa@...dia.com, jgg@...pe.ca,
 linux-arm-kernel@...ts.infradead.org, iommu@...ts.linux.dev,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-tegra@...r.kernel.org
Subject: Re: [PATCH V8 3/4] dt-bindings: iommu: Add NVIDIA Tegra CMDQV support



On 13/01/2026 05:49, Ashish Mhetre wrote:
> The Command Queue Virtualization (CMDQV) hardware is part of the
> SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in
> virtualizing the command queue for the SMMU.
> 
> Add a new device tree binding document for nvidia,tegra264-cmdqv.
> 
> Also update the arm,smmu-v3 binding to include an optional nvidia,cmdqv
> property. This property is a phandle to the CMDQV device node, allowing
> the SMMU driver to associate with its corresponding CMDQV instance.
> Restrict this property usage to Nvidia Tegra264 only.
> 
> Reviewed-by: Rob Herring (Arm) <robh@...nel.org>
> Acked-by: Nicolin Chen <nicolinc@...dia.com>
> Signed-off-by: Ashish Mhetre <amhetre@...dia.com>
> ---
>   .../bindings/iommu/arm,smmu-v3.yaml           | 27 +++++++++++-
>   .../bindings/iommu/nvidia,tegra264-cmdqv.yaml | 42 +++++++++++++++++++
>   2 files changed, 68 insertions(+), 1 deletion(-)
>   create mode 100644 Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
> 
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> index 75fcf4cb52d9..82957334bea2 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> @@ -20,7 +20,12 @@ properties:
>     $nodename:
>       pattern: "^iommu@[0-9a-f]*"
>     compatible:
> -    const: arm,smmu-v3
> +    oneOf:
> +      - const: arm,smmu-v3
> +      - items:
> +          - enum:
> +              - nvidia,tegra264-smmu
> +          - const: arm,smmu-v3
>   
>     reg:
>       maxItems: 1
> @@ -58,6 +63,15 @@ properties:
>   
>     msi-parent: true
>   
> +  nvidia,cmdqv:
> +    description: |
> +      A phandle to its pairing CMDQV extension for an implementation on NVIDIA
> +      Tegra SoC.
> +
> +      If this property is absent, CMDQ-Virtualization won't be used and SMMU
> +      will only use its own CMDQ.
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +
>     hisilicon,broken-prefetch-cmd:
>       type: boolean
>       description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
> @@ -69,6 +83,17 @@ properties:
>         register access with page 0 offsets. Set for Cavium ThunderX2 silicon that
>         doesn't support SMMU page1 register space.
>   
> +allOf:
> +  - if:
> +      not:
> +        properties:
> +          compatible:
> +            contains:
> +              const: nvidia,tegra264-smmu
> +    then:
> +      properties:
> +        nvidia,cmdqv: false
> +
>   required:
>     - compatible
>     - reg
> diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
> new file mode 100644
> index 000000000000..3f5006a59805
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
> @@ -0,0 +1,42 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iommu/nvidia,tegra264-cmdqv.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra264 CMDQV
> +
> +description:
> +  The CMDQ-Virtualization hardware block is part of the SMMUv3 implementation
> +  on Tegra264 SoCs. It assists in virtualizing the command queue for the SMMU.
> +
> +maintainers:
> +  - Nicolin Chen <nicolinc@...dia.com>
> +
> +properties:
> +  compatible:
> +    const: nvidia,tegra264-cmdqv
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    cmdqv@...0000 {
> +            compatible = "nvidia,tegra264-cmdqv";
> +            reg = <0x5200000 0x830000>;
> +            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> +    };

Looks good to me!

Reviewed-by: Jon Hunter <jonathanh@...dia.com>

Cheers
Jon

-- 
nvpublic