| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <CAMuHMdW+ZvuJg0ivCM2CHJkRBdx8sgiku1jGgrD_mcO4yV9vHg@mail.gmail.com>
Date: Wed, 14 Jan 2026 16:23:08 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Tommaso Merciai <tommaso.merciai.xr@...renesas.com>
Cc: tomm.merciai@...il.com, linux-renesas-soc@...r.kernel.org,
biju.das.jz@...renesas.com, Andrzej Hajda <andrzej.hajda@...el.com>,
Neil Armstrong <neil.armstrong@...aro.org>, Robert Foss <rfoss@...nel.org>,
Laurent Pinchart <Laurent.pinchart@...asonboard.com>, Jonas Karlman <jonas@...boo.se>,
Jernej Skrabec <jernej.skrabec@...il.com>, David Airlie <airlied@...il.com>,
Simona Vetter <simona@...ll.ch>, Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
Magnus Damm <magnus.damm@...il.com>, dri-devel@...ts.freedesktop.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org
Subject: Re: [PATCH 21/22] arm64: dts: renesas: r9a09g047: Add DU{0,1} and DSI nodes
Hi Tommaso,
On Wed, 26 Nov 2025 at 15:11, Tommaso Merciai
<tommaso.merciai.xr@...renesas.com> wrote:
> Add DU0, DU1, DSI nodes to RZ/RZG3E SoC DTSI.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@...renesas.com>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> +
> + du0: du0@...60000 {
display@
> + compatible = "renesas,r9a09g047-du0";
I doubt this compatible value will survive review...
> + reg = <0 0x16460000 0 0x10000>;
> + interrupts = <GIC_SPI 882 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 0xed>,
> + <&cpg CPG_MOD 0xee>,
> + <&cpg CPG_MOD 0xef>;
> + clock-names = "aclk", "pclk", "vclk";
> + power-domains = <&cpg>;
> + resets = <&cpg 0xdc>;
> + renesas,vsps = <&vspd0 0>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + du0_out_dsi0: endpoint {
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + du0_out_lvds0: endpoint {
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + du0_out_lvds1: endpoint {
> + };
> + };
> + };
> + };
> +
> + du1: du1@...90000 {
display@
> + compatible = "renesas,r9a09g047-du1";
I doubt this compatible value will survive review...
> + reg = <0 0x16490000 0 0x10000>;
> + interrupts = <GIC_SPI 922 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 0x1a8>,
> + <&cpg CPG_MOD 0x1a9>,
> + <&cpg CPG_MOD 0x1aa>;
> + clock-names = "aclk", "pclk", "vclk";
> + power-domains = <&cpg>;
> + resets = <&cpg 0x11e>;
> + renesas,vsps = <&vspd1 0>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + du1_out_dsi0: endpoint {
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + du1_out_lvds0: endpoint {
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
I expect this will become "port@3" and "reg = <3>" with a unified compatible
value?
> + du1_out_rgb0: endpoint {
> + };
> + };
> +
> + };
> + };
> +
> fcpvd0: fcp@...70000 {
> compatible = "renesas,r9a09g047-fcpvd",
> "renesas,fcpv";
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Powered by blists - more mailing lists