Message-ID: <CA+V-a8s0gPbe2ffmN1G_7ibVL4+=FKUEQZu3_CwQL=U0T3--DQ@mail.gmail.com>
Date: Wed, 14 Jan 2026 20:53:12 +0000
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Conor Dooley <conor@...nel.org>, Linus Walleij <linus.walleij@...aro.org>, 
	Geert Uytterhoeven <geert+renesas@...der.be>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
	Conor Dooley <conor+dt@...nel.org>, Magnus Damm <magnus.damm@...il.com>, 
	linux-renesas-soc@...r.kernel.org, linux-gpio@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: renesas,r9a09g077: Document pin
 configuration properties

Hi All,

Sorry for the late reply.

On Mon, Dec 8, 2025 at 6:01 PM Conor Dooley <conor@...nel.org> wrote:
>
> On Mon, Dec 08, 2025 at 10:36:04AM +0000, Lad, Prabhakar wrote:
> > Hi Conor,
> >
> > Sorry for the delayed response. Ive got feedback from the HW team.
> >
> > On Fri, Oct 17, 2025 at 4:33 PM Lad, Prabhakar
> > <prabhakar.csengg@...il.com> wrote:
> > >
> > > Hi Conor,
> > >
> > > Thank you for the review.
> > >
> > > On Thu, Oct 16, 2025 at 5:41 PM Conor Dooley <conor@...nel.org> wrote:
> > > >
> > > > On Tue, Oct 14, 2025 at 08:11:20PM +0100, Prabhakar wrote:
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > > > >
> > > > > Document the pin configuration properties supported by the RZ/T2H pinctrl
> > > > > driver. The RZ/T2H SoC supports configuring various electrical properties
> > > > > through the DRCTLm (I/O Buffer Function Switching) registers.
> > > > >
> > > > > Add documentation for the following standard properties:
> > > > > - bias-disable, bias-pull-up, bias-pull-down: Control internal
> > > > >   pull-up/pull-down resistors (3 options: no pull, pull-up, pull-down)
> > > > > - input-schmitt-enable, input-schmitt-disable: Control Schmitt trigger
> > > > >   input
> > > > > - slew-rate: Control output slew rate (2 options: slow/fast)
> > > > >
> > > > > Add documentation for the custom property:
> > > > > - renesas,drive-strength: Control output drive strength using discrete
> > > > >   levels (0-3) representing low, medium, high, and ultra high strength.
> > > > >   This custom property is needed because the hardware uses fixed discrete
> > > > >   levels rather than configurable milliamp values.
> > > > >
> > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > > > > ---
> > > > >  .../bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml | 13 +++++++++++++
> > > > >  1 file changed, 13 insertions(+)
> > > > >
> > > > > diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> > > > > index 36d665971484..9085d5cfb1c8 100644
> > > > > --- a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> > > > > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
> > > > > @@ -72,6 +72,19 @@ definitions:
> > > > >        input: true
> > > > >        input-enable: true
> > > > >        output-enable: true
> > > > > +      bias-disable: true
> > > > > +      bias-pull-down: true
> > > > > +      bias-pull-up: true
> > > > > +      input-schmitt-enable: true
> > > > > +      input-schmitt-disable: true
> > > > > +      slew-rate:
> > > > > +        enum: [0, 1]
> > > >
> > > > What are the meanings of "0" and "1" for slew rate? Why isn't this given
> > > I'll add a description for it (0 = slow, 1 = fast) and the same values
> > > are programmed in the register to configure the slew rate.
> > >
> > > > as the actual rates? The docs surely give more detail than just "slow"
> > > > and "fast".
> > > You mean to represent slew-rate in some sort of a unit?
> > >
> > Based on the comments from the HW team, there is no numerical
> > definition to represent slow/fast It only defines a relative
> > relationship.
> > > >
> > > > > +      renesas,drive-strength:
> > > > > +        description:
> > > > > +          Drive strength configuration value. Valid values are 0 to 3, representing
> > > > > +          increasing drive strength from low, medium, high and ultra high.
> > > >
I got the feedback from the HW team "The RZ/T2H drive strength
(driving ability) is expressed using abstract levels such as Low,
Middle, and High. These values do not correspond directly to specific
mA units. To determine how much current the pin can actually drive,
the engineer must refer to the electrical characteristics table.
Therefore, the drive strength in RZ/T2H is a parameter that switches
the internal output transistor mode rather than directly representing
a physical drive current.
Consequently, expressing RZ/T2H drive strength in milli- or
micro-amps, as suggested by the reviewer, is inappropriate. To
accurately reflect the SoC's hardware specification, introducing a
custom property is essential."

To elaborate more on this [0] has the tables which are extracted from
the HW manual [1] (which needs login). For example, considering SDHI
referring to table 58.39 in [0] the drive strength can be calculated
for SD using  I = C × (delta V / deltaT).

For (SD) SDR104/ (eMMC)HS200 case C = 15pf, VDD1833 = 1.8 V and
rise/fall time 1ns that would result to 27.000 mA
For (SD) SDR50, SDR25, SDR12 (eMMC) High Speed SDR case C = 20pf,
VDD1833 = 1.8 V and rise/fall time 2ns that would result to 18.000 mA

As the drive strength is varying based on the speeds this cannot be
tied up to the fixed value. Hence to simplify the Table 58.11 in [0]
lists out the required drive strength and slew rate based on operating
voltage levels.

[0] https://gist.github.com/prabhakarlad/026a73c3a3922da2b88d0578db68276c
[1] https://www.renesas.com/en/document/mah/rzt2h-and-rzn2h-groups-users-manual-hardware?language=en&r=25567515

Please share your thoughts.

Cheers,
Prabhakar

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