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Message-ID: <0eb5086c-39f1-4cf3-aa71-440036930052@gmail.com>
Date: Wed, 14 Jan 2026 09:16:58 +0100
From: Matthias Brugger <matthias.bgg@...il.com>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
linux-mediatek@...ts.infradead.org
Cc: robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
mturquette@...libre.com, sboyd@...nel.org, matthias.bgg@...il.com,
ulf.hansson@...aro.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-pm@...r.kernel.org,
kernel@...labora.com
Subject: Re: [PATCH 1/5] dt-bindings: clock: mediatek,mt7622-pciesys: Remove
syscon compatible
On 13/1/26 12:00, AngeloGioacchino Del Regno wrote:
> The PCIESYS register space contains a pure clock controller, which
> has no system controller register, so this definitely doesn't need
> any "syscon" compatible.
>
> As a side note, luckily no devicetree ever added the syscon string
> to PCIESYS clock controller node compatibles, so this also resolves
> a dtbs_check warning for mt7622.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@...il.com>
> ---
> .../bindings/clock/mediatek,mt7622-pciesys.yaml | 10 ++++------
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml
> index 9c3913f9092c..c77111d10f90 100644
> --- a/Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml
> @@ -14,11 +14,9 @@ maintainers:
>
> properties:
> compatible:
> - oneOf:
> - - items:
> - - const: mediatek,mt7622-pciesys
> - - const: syscon
> - - const: mediatek,mt7629-pciesys
> + enum:
> + - mediatek,mt7622-pciesys
> + - mediatek,mt7629-pciesys
>
> reg:
> maxItems: 1
> @@ -40,7 +38,7 @@ additionalProperties: false
> examples:
> - |
> clock-controller@...00800 {
> - compatible = "mediatek,mt7622-pciesys", "syscon";
> + compatible = "mediatek,mt7622-pciesys";
> reg = <0x1a100800 0x1000>;
> #clock-cells = <1>;
> #reset-cells = <1>;
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