lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <aWdbPze-f_2_5EbL@smile.fi.intel.com>
Date: Wed, 14 Jan 2026 11:00:47 +0200
From: Andy Shevchenko <andriy.shevchenko@...el.com>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Cc: jic23@...nel.org, dlechner@...libre.com, nuno.sa@...log.com,
	andy@...nel.org, arnd@...db.de, gregkh@...uxfoundation.org,
	srini@...nel.org, vkoul@...nel.org, neil.armstrong@...aro.org,
	sre@...nel.org, sboyd@...nel.org, krzk@...nel.org,
	dmitry.baryshkov@....qualcomm.com, quic_wcheng@...cinc.com,
	melody.olvera@....qualcomm.com, quic_nsekar@...cinc.com,
	ivo.ivanov.ivanov1@...il.com, abelvesa@...nel.org,
	luca.weiss@...rphone.com, konrad.dybcio@....qualcomm.com,
	mitltlatltl@...il.com, krishna.kurapati@....qualcomm.com,
	linux-arm-msm@...r.kernel.org, linux-iio@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org,
	linux-pm@...r.kernel.org, kernel@...labora.com
Subject: Re: [PATCH v7 05/10] nvmem: qcom-spmi-sdam: Migrate to
 devm_spmi_subdevice_alloc_and_add()

On Wed, Jan 14, 2026 at 09:59:40AM +0100, AngeloGioacchino Del Regno wrote:
> Il 14/01/26 09:56, Andy Shevchenko ha scritto:
> > On Wed, Jan 14, 2026 at 09:39:52AM +0100, AngeloGioacchino Del Regno wrote:
> > > Some Qualcomm PMICs integrate a SDAM device, internally located in
> > > a specific address range reachable through SPMI communication.
> > > 
> > > Instead of using the parent SPMI device (the main PMIC) as a kind
> > > of syscon in this driver, register a new SPMI sub-device for SDAM
> > > and initialize its own regmap with this sub-device's specific base
> > > address, retrieved from the devicetree.
> > > 
> > > This allows to stop manually adding the register base address to
> > > every R/W call in this driver, as this can be, and is now, handled
> > > by the regmap API instead.

...

> > > +	struct regmap_config sdam_regmap_config = {
> > > +		.reg_bits = 16,
> > > +		.val_bits = 8,
> > 
> > > +		.max_register = 0x100,
> > 
> > Are you sure? This might be a bad naming, but here max == the last accessible.
> > I bet it has to be 0xff (but since the address is 16-bit it might be actually
> > 257 registers, but sounds very weird).
> 
> Yes, I'm sure.

So, what is resided on address 0x100 ?

> > > +		.fast_io = true,
> > > +	};


-- 
With Best Regards,
Andy Shevchenko



Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ