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Message-ID: <647b4acc-3310-4329-ac7a-77e86bab74a3@collabora.com>
Date: Wed, 14 Jan 2026 10:09:45 +0100
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Andy Shevchenko <andriy.shevchenko@...el.com>
Cc: jic23@...nel.org, dlechner@...libre.com, nuno.sa@...log.com,
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dmitry.baryshkov@....qualcomm.com, quic_wcheng@...cinc.com,
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Subject: Re: [PATCH v7 05/10] nvmem: qcom-spmi-sdam: Migrate to
devm_spmi_subdevice_alloc_and_add()
Il 14/01/26 10:07, Andy Shevchenko ha scritto:
> On Wed, Jan 14, 2026 at 10:03:57AM +0100, AngeloGioacchino Del Regno wrote:
>> Il 14/01/26 10:00, Andy Shevchenko ha scritto:
>>> On Wed, Jan 14, 2026 at 09:59:40AM +0100, AngeloGioacchino Del Regno wrote:
>>>> Il 14/01/26 09:56, Andy Shevchenko ha scritto:
>>>>> On Wed, Jan 14, 2026 at 09:39:52AM +0100, AngeloGioacchino Del Regno wrote:
>
> ...
>
>>>>>> + struct regmap_config sdam_regmap_config = {
>>>>>> + .reg_bits = 16,
>>>>>> + .val_bits = 8,
>>>>>
>>>>>> + .max_register = 0x100,
>>>>>
>>>>> Are you sure? This might be a bad naming, but here max == the last accessible.
>>>>> I bet it has to be 0xff (but since the address is 16-bit it might be actually
>>>>> 257 registers, but sounds very weird).
>>>>
>>>> Yes, I'm sure.
>>>
>>> So, what is resided on address 0x100 ?
>>
>> I don't remember, this is research from around 5 months ago, when I've sent
>> the v1 of this.
>>
>> If you really want though, I can incorrectly set max_register to 0xff.
>
> Why incorrectly? Can you dig into the datasheet and check, please? We don't
> know what is the 0x100 address means.
>
I don't have any datasheets for Qualcomm IPs.
Cheers,
Angelo
>>>>>> + .fast_io = true,
>>>>>> + };
>
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