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Message-ID: <20260114103846.687338-1-pshete@nvidia.com>
Date: Wed, 14 Jan 2026 10:38:44 +0000
From: Prathamesh Shete <pshete@...dia.com>
To: <linusw@...nel.org>, <brgl@...nel.org>, <krzk+dt@...nel.org>,
<conor+dt@...nel.org>, <thierry.reding@...il.com>, <jonathanh@...dia.com>,
<robh@...nel.org>, <linux-gpio@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
CC: <pshete@...dia.com>
Subject: [PATCH 1/3] dt-bindings: gpio: Add Tegra264 support
Extend the existing Tegra186 GPIO controller device tree bindings with
support for the GPIO controller found on Tegra264. The number of pins
is slightly different, but the programming model remains the same.
Add a new header, include/dt-bindings/gpio/tegra264-gpio.h,
that defines port IDs as well as the TEGRA264_MAIN_GPIO() helper,
both of which are used in conjunction to create a unique specifier
for each pin.
Document nvidia,pmc property referencing the PMC node providing the
parent interrupt domain. GPIO driver uses this to select the correct
PMC,falling back to compatible-based lookup only if the phandle is
absent.
Signed-off-by: Prathamesh Shete <pshete@...dia.com>
---
.../bindings/gpio/nvidia,tegra186-gpio.yaml | 10 +++
include/dt-bindings/gpio/tegra264-gpio.h | 61 +++++++++++++++++++
2 files changed, 71 insertions(+)
create mode 100644 include/dt-bindings/gpio/tegra264-gpio.h
diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml
index 2bd620a1099b..93150504c03c 100644
--- a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml
@@ -86,6 +86,9 @@ properties:
- nvidia,tegra234-gpio
- nvidia,tegra234-gpio-aon
- nvidia,tegra256-gpio
+ - nvidia,tegra264-gpio
+ - nvidia,tegra264-gpio-uphy
+ - nvidia,tegra264-gpio-aon
reg-names:
items:
@@ -110,6 +113,10 @@ properties:
ports, in the order the HW manual describes them. The number of entries
required varies depending on compatible value.
+ nvidia,pmc:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Phandle to the PMC node providing the parent interrupt domain.
+
gpio-controller: true
gpio-ranges:
@@ -157,6 +164,8 @@ allOf:
- nvidia,tegra194-gpio
- nvidia,tegra234-gpio
- nvidia,tegra256-gpio
+ - nvidia,tegra264-gpio
+ - nvidia,tegra264-gpio-uphy
then:
properties:
interrupts:
@@ -171,6 +180,7 @@ allOf:
- nvidia,tegra186-gpio-aon
- nvidia,tegra194-gpio-aon
- nvidia,tegra234-gpio-aon
+ - nvidia,tegra264-gpio-aon
then:
properties:
interrupts:
diff --git a/include/dt-bindings/gpio/tegra264-gpio.h b/include/dt-bindings/gpio/tegra264-gpio.h
new file mode 100644
index 000000000000..d7baceace474
--- /dev/null
+++ b/include/dt-bindings/gpio/tegra264-gpio.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */
+
+/*
+ * This header provides constants for binding nvidia,tegra264-gpio*.
+ *
+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.
+ *
+ * The second cell contains standard flag values specified in gpio.h.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_TEGRA264_GPIO_H
+#define _DT_BINDINGS_GPIO_TEGRA264_GPIO_H
+
+#include <dt-bindings/gpio/gpio.h>
+
+/* GPIOs implemented by main GPIO controller */
+#define TEGRA264_MAIN_GPIO_PORT_T 0
+#define TEGRA264_MAIN_GPIO_PORT_U 1
+#define TEGRA264_MAIN_GPIO_PORT_V 2
+#define TEGRA264_MAIN_GPIO_PORT_W 3
+#define TEGRA264_MAIN_GPIO_PORT_AL 4
+#define TEGRA264_MAIN_GPIO_PORT_Y 5
+#define TEGRA264_MAIN_GPIO_PORT_Z 6
+#define TEGRA264_MAIN_GPIO_PORT_X 7
+#define TEGRA264_MAIN_GPIO_PORT_H 8
+#define TEGRA264_MAIN_GPIO_PORT_J 9
+#define TEGRA264_MAIN_GPIO_PORT_K 10
+#define TEGRA264_MAIN_GPIO_PORT_L 11
+#define TEGRA264_MAIN_GPIO_PORT_M 12
+#define TEGRA264_MAIN_GPIO_PORT_P 13
+#define TEGRA264_MAIN_GPIO_PORT_Q 14
+#define TEGRA264_MAIN_GPIO_PORT_R 15
+#define TEGRA264_MAIN_GPIO_PORT_S 16
+#define TEGRA264_MAIN_GPIO_PORT_F 17
+#define TEGRA264_MAIN_GPIO_PORT_G 18
+
+#define TEGRA264_MAIN_GPIO(port, offset) \
+ ((TEGRA264_MAIN_GPIO_PORT_##port * 8) + (offset))
+
+/* GPIOs implemented by AON GPIO controller */
+#define TEGRA264_AON_GPIO_PORT_AA 0
+#define TEGRA264_AON_GPIO_PORT_BB 1
+#define TEGRA264_AON_GPIO_PORT_CC 2
+#define TEGRA264_AON_GPIO_PORT_DD 3
+#define TEGRA264_AON_GPIO_PORT_EE 4
+
+#define TEGRA264_AON_GPIO(port, offset) \
+ ((TEGRA264_AON_GPIO_PORT_##port * 8) + (offset))
+
+#define TEGRA264_UPHY_GPIO_PORT_A 0
+#define TEGRA264_UPHY_GPIO_PORT_B 1
+#define TEGRA264_UPHY_GPIO_PORT_C 2
+#define TEGRA264_UPHY_GPIO_PORT_D 3
+#define TEGRA264_UPHY_GPIO_PORT_E 4
+
+#define TEGRA264_UPHY_GPIO(port, offset) \
+ ((TEGRA264_UPHY_GPIO_PORT_##port * 8) + (offset))
+
+#endif
--
2.25.1
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