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Message-ID: <aWj/loNWNNNQTLPQ@lizhi-Precision-Tower-5810>
Date: Thu, 15 Jan 2026 09:54:14 -0500
From: Frank Li <Frank.li@....com>
To: Koichiro Den <den@...inux.co.jp>
Cc: jingoohan1@...il.com, mani@...nel.org, lpieralisi@...nel.org,
kwilczynski@...nel.org, robh@...nel.org, bhelgaas@...gle.com,
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Subject: Re: [PATCH v8 3/5] PCI: dwc: Advertise dynamic inbound mapping
support
On Thu, Jan 15, 2026 at 05:49:26PM +0900, Koichiro Den wrote:
> The DesignWare EP core has supported updating the inbound iATU mapping
> for an already configured BAR (i.e. allowing pci_epc_set_bar() to be
> called again without a prior pci_epc_clear_bar()) since commit
> 4284c88fff0e ("PCI: designware-ep: Allow pci_epc_set_bar() update
> inbound map address").
>
> Now that this capability is exposed via the dynamic_inbound_mapping EPC
> feature bit, set it for DWC-based EP glue drivers using a common
> initializer macro to avoid duplicating the same flag in each driver.
>
> Note that pci-layerscape-ep.c is untouched. It currently constructs the
> feature struct dynamically in ls_pcie_ep_init(). Once converted to a
> static feature definition, it will use DWC_EPC_COMMON_FEATURES as well.
>
> Signed-off-by: Koichiro Den <den@...inux.co.jp>
> ---
Reviewed-by: Frank Li <Frank.Li@....com>
> drivers/pci/controller/dwc/pci-dra7xx.c | 1 +
> drivers/pci/controller/dwc/pci-imx6.c | 3 +++
> drivers/pci/controller/dwc/pci-keystone.c | 1 +
> drivers/pci/controller/dwc/pcie-artpec6.c | 1 +
> drivers/pci/controller/dwc/pcie-designware-plat.c | 1 +
> drivers/pci/controller/dwc/pcie-designware.h | 3 +++
> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 2 ++
> drivers/pci/controller/dwc/pcie-keembay.c | 1 +
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 +
> drivers/pci/controller/dwc/pcie-rcar-gen4.c | 1 +
> drivers/pci/controller/dwc/pcie-stm32-ep.c | 1 +
> drivers/pci/controller/dwc/pcie-tegra194.c | 1 +
> drivers/pci/controller/dwc/pcie-uniphier-ep.c | 2 ++
> 13 files changed, 19 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
> index 01cfd9aeb0b8..d5d26229063f 100644
> --- a/drivers/pci/controller/dwc/pci-dra7xx.c
> +++ b/drivers/pci/controller/dwc/pci-dra7xx.c
> @@ -424,6 +424,7 @@ static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> }
>
> static const struct pci_epc_features dra7xx_pcie_epc_features = {
> + DWC_EPC_COMMON_FEATURES,
> .linkup_notifier = true,
> .msi_capable = true,
> };
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 4668fc9648bf..f28e335bbbfa 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -1387,6 +1387,7 @@ static int imx_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> }
>
> static const struct pci_epc_features imx8m_pcie_epc_features = {
> + DWC_EPC_COMMON_FEATURES,
> .msi_capable = true,
> .bar[BAR_1] = { .type = BAR_RESERVED, },
> .bar[BAR_3] = { .type = BAR_RESERVED, },
> @@ -1396,6 +1397,7 @@ static const struct pci_epc_features imx8m_pcie_epc_features = {
> };
>
> static const struct pci_epc_features imx8q_pcie_epc_features = {
> + DWC_EPC_COMMON_FEATURES,
> .msi_capable = true,
> .bar[BAR_1] = { .type = BAR_RESERVED, },
> .bar[BAR_3] = { .type = BAR_RESERVED, },
> @@ -1416,6 +1418,7 @@ static const struct pci_epc_features imx8q_pcie_epc_features = {
> * BAR5 | Enable | 32-bit | 64 KB | Programmable Size
> */
> static const struct pci_epc_features imx95_pcie_epc_features = {
> + DWC_EPC_COMMON_FEATURES,
> .msi_capable = true,
> .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_64K, },
> .align = SZ_4K,
> diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
> index f86d9111f863..20fa4dadb82a 100644
> --- a/drivers/pci/controller/dwc/pci-keystone.c
> +++ b/drivers/pci/controller/dwc/pci-keystone.c
> @@ -930,6 +930,7 @@ static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> }
>
> static const struct pci_epc_features ks_pcie_am654_epc_features = {
> + DWC_EPC_COMMON_FEATURES,
> .msi_capable = true,
> .msix_capable = true,
> .bar[BAR_0] = { .type = BAR_RESERVED, },
> diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
> index f4a136ee2daf..e994b75986c3 100644
> --- a/drivers/pci/controller/dwc/pcie-artpec6.c
> +++ b/drivers/pci/controller/dwc/pcie-artpec6.c
> @@ -370,6 +370,7 @@ static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> }
>
> static const struct pci_epc_features artpec6_pcie_epc_features = {
> + DWC_EPC_COMMON_FEATURES,
> .msi_capable = true,
> };
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
> index 12f41886c65d..8530746ec5cb 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-plat.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
> @@ -61,6 +61,7 @@ static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> }
>
> static const struct pci_epc_features dw_plat_pcie_epc_features = {
> + DWC_EPC_COMMON_FEATURES,
> .msi_capable = true,
> .msix_capable = true,
> };
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index f87c67a7a482..4df0cc44faab 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -305,6 +305,9 @@
> /* Default eDMA LLP memory size */
> #define DMA_LLP_MEM_SIZE PAGE_SIZE
>
> +/* Common struct pci_epc_feature bits among DWC EP glue drivers */
> +#define DWC_EPC_COMMON_FEATURES .dynamic_inbound_mapping = true
> +
> struct dw_pcie;
> struct dw_pcie_rp;
> struct dw_pcie_ep;
> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> index 352f513ebf03..f985a934a137 100644
> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> @@ -384,6 +384,7 @@ static int rockchip_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> }
>
> static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = {
> + DWC_EPC_COMMON_FEATURES,
> .linkup_notifier = true,
> .msi_capable = true,
> .msix_capable = true,
> @@ -404,6 +405,7 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = {
> * BARs) would be overwritten, resulting in (all other BARs) no longer working.
> */
> static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = {
> + DWC_EPC_COMMON_FEATURES,
> .linkup_notifier = true,
> .msi_capable = true,
> .msix_capable = true,
> diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c
> index 60e74ac782af..2666a9c3d67e 100644
> --- a/drivers/pci/controller/dwc/pcie-keembay.c
> +++ b/drivers/pci/controller/dwc/pcie-keembay.c
> @@ -309,6 +309,7 @@ static int keembay_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> }
>
> static const struct pci_epc_features keembay_pcie_epc_features = {
> + DWC_EPC_COMMON_FEATURES,
> .msi_capable = true,
> .msix_capable = true,
> .bar[BAR_0] = { .only_64bit = true, },
> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> index f1bc0ac81a92..5e990c7a5879 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> @@ -820,6 +820,7 @@ static void qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep *pcie_ep)
> }
>
> static const struct pci_epc_features qcom_pcie_epc_features = {
> + DWC_EPC_COMMON_FEATURES,
> .linkup_notifier = true,
> .msi_capable = true,
> .align = SZ_4K,
> diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> index 80778917d2dd..a6912e85e4dd 100644
> --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> @@ -420,6 +420,7 @@ static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> }
>
> static const struct pci_epc_features rcar_gen4_pcie_epc_features = {
> + DWC_EPC_COMMON_FEATURES,
> .msi_capable = true,
> .bar[BAR_1] = { .type = BAR_RESERVED, },
> .bar[BAR_3] = { .type = BAR_RESERVED, },
> diff --git a/drivers/pci/controller/dwc/pcie-stm32-ep.c b/drivers/pci/controller/dwc/pcie-stm32-ep.c
> index 2cecf32d2b0f..c1944b40ce02 100644
> --- a/drivers/pci/controller/dwc/pcie-stm32-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-stm32-ep.c
> @@ -70,6 +70,7 @@ static int stm32_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> }
>
> static const struct pci_epc_features stm32_pcie_epc_features = {
> + DWC_EPC_COMMON_FEATURES,
> .msi_capable = true,
> .align = SZ_64K,
> };
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 0ddeef70726d..06571d806ab3 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1988,6 +1988,7 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> }
>
> static const struct pci_epc_features tegra_pcie_epc_features = {
> + DWC_EPC_COMMON_FEATURES,
> .linkup_notifier = true,
> .msi_capable = true,
> .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,
> diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> index d6e73811216e..d52753060970 100644
> --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> @@ -420,6 +420,7 @@ static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = {
> .init = uniphier_pcie_pro5_init_ep,
> .wait = NULL,
> .features = {
> + DWC_EPC_COMMON_FEATURES,
> .linkup_notifier = false,
> .msi_capable = true,
> .msix_capable = false,
> @@ -438,6 +439,7 @@ static const struct uniphier_pcie_ep_soc_data uniphier_nx1_data = {
> .init = uniphier_pcie_nx1_init_ep,
> .wait = uniphier_pcie_nx1_wait_ep,
> .features = {
> + DWC_EPC_COMMON_FEATURES,
> .linkup_notifier = false,
> .msi_capable = true,
> .msix_capable = false,
> --
> 2.51.0
>
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