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Message-ID: <20260115152831.00001950@huawei.com>
Date: Thu, 15 Jan 2026 15:28:31 +0000
From: Jonathan Cameron <jonathan.cameron@...wei.com>
To: Terry Bowman <terry.bowman@....com>
CC: <dave@...olabs.net>, <dave.jiang@...el.com>, <alison.schofield@...el.com>,
<dan.j.williams@...el.com>, <bhelgaas@...gle.com>, <shiju.jose@...wei.com>,
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<rrichter@....com>, <dan.carpenter@...aro.org>,
<PradeepVineshReddy.Kodamati@....com>, <lukas@...ner.de>,
<Benjamin.Cheatham@....com>, <sathyanarayanan.kuppuswamy@...ux.intel.com>,
<linux-cxl@...r.kernel.org>, <vishal.l.verma@...el.com>, <alucerop@....com>,
<ira.weiny@...el.com>, <linux-kernel@...r.kernel.org>,
<linux-pci@...r.kernel.org>
Subject: Re: [PATCH v14 24/34] cxl/port: Move endpoint component register
management to cxl_port
On Wed, 14 Jan 2026 12:20:45 -0600
Terry Bowman <terry.bowman@....com> wrote:
> From: Dan Williams <dan.j.williams@...el.com>
>
> In preparation for generic protocol error handling across CXL endpoints,
> whether they be memory expander class devices or accelerators, drop the
> endpoint component management from cxl_dev_state.
>
> Organize all CXL port component management through the common cxl_port
> driver.
>
> Note that the end game is that drivers/cxl/core/ras.c loses all
> dependencies on a 'struct cxl_dev_state' parameter and operates only on
> port resources. The removal of component register mapping from cxl_pci is
> an incremental step towards that.
>
> Signed-off-by: Dan Williams <dan.j.williams@...el.com>
> Reviewed-by: Terry Bowman <terry.bowman@....com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@...wei.com>
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