linux-kernel - Re: [PATCH] PCI/sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

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Message-ID: <aWg0uytowyzbOBMX@inochi.infowork>
Date: Thu, 15 Jan 2026 08:29:18 +0800
From: Inochi Amaoto <inochiama@...il.com>
To: Manivannan Sadhasivam <mani@...nel.org>, 
	Inochi Amaoto <inochiama@...il.com>
Cc: Lorenzo Pieralisi <lpieralisi@...nel.org>, 
	Krzysztof Wilczyński <kwilczynski@...nel.org>, Rob Herring <robh@...nel.org>, 
	Bjorn Helgaas <bhelgaas@...gle.com>, Chen Wang <unicorn_wang@...look.com>, 
	Christophe JAILLET <christophe.jaillet@...adoo.fr>, Han Gao <rabenda.cn@...il.com>, linux-pci@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Yixun Lan <dlan@...too.org>, Longbin Li <looong.bin@...il.com>, 
	Han Gao <gaohan@...as.ac.cn>
Subject: Re: [PATCH] PCI/sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root
 Ports

On Tue, Jan 13, 2026 at 08:23:17PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Jan 09, 2026 at 12:07:54PM +0800, Inochi Amaoto wrote:
> > Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> > states for devicetree platforms") force enable ASPM on all device tree
> > platform, the SG2042 root port breaks as it advertises L0s and L1
> > capabilities without supporting it.
> > 
> > Override the L0s and L1 Support advertised in Link Capabilities in
> > the LINKCTL register of SG2042 Root Ports, so it doesn't try to enable
> > those states.
> > 
> 
> You need to disable L0s and L1 capabilities in LNKCAP. LNKCTL change is
> volatile, since both PCI core and userspace can override it as long as the
> capabilities are supported.
> 
> - Mani
> 

Good to know, I will switch to the LNKCAP.

Regards,
Inochi

> > Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042")
> > Signed-off-by: Inochi Amaoto <inochiama@...il.com>
> > Tested-by: Han Gao <gaohan@...as.ac.cn>
> > ---
> > Change from original patch:
> > 1. use driver to mask the ASPM advertisement
> > 
> > Separate from the folloing patch
> > - https://lore.kernel.org/all/20251225100530.1301625-1-inochiama@gmail.com
> > ---
> >  drivers/pci/controller/cadence/pcie-sg2042.c | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> > 
> > diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c
> > index 0c50c74d03ee..9c42e05d3c46 100644
> > --- a/drivers/pci/controller/cadence/pcie-sg2042.c
> > +++ b/drivers/pci/controller/cadence/pcie-sg2042.c
> > @@ -32,6 +32,15 @@ static struct pci_ops sg2042_pcie_child_ops = {
> >  	.write		= pci_generic_config_write,
> >  };
> > 
> > +static void sg2042_pcie_disable_l0s_l1(struct cdns_pcie *pcie)
> > +{
> > +	u32 val;
> > +
> > +	val = cdns_pcie_rp_readw(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCTL);
> > +	val &= ~PCI_EXP_LNKCTL_ASPMC;
> > +	cdns_pcie_rp_writew(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCTL, val);
> > +}
> > +
> >  static int sg2042_pcie_probe(struct platform_device *pdev)
> >  {
> >  	struct device *dev = &pdev->dev;
> > @@ -68,6 +77,8 @@ static int sg2042_pcie_probe(struct platform_device *pdev)
> >  		return ret;
> >  	}
> > 
> > +	sg2042_pcie_disable_l0s_l1(pcie);
> > +
> >  	return 0;
> >  }
> > 
> > --
> > 2.52.0
> > 
> 
> -- 
> மணிவண்ணன் சதாசிவம்