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Message-ID: <10a102b9-1dd1-c5ca-66e4-f02794a84a93@kernel.org>
Date: Wed, 14 Jan 2026 17:39:02 -0700 (MST)
From: Paul Walmsley <pjw@...nel.org>
To: Naohiko Shimizu <naohiko.shimizu@...il.com>
cc: pjw@...nel.org, palmer@...belt.com, aou@...s.berkeley.edu, alex@...ti.fr, 
    anup@...infault.org, atish.patra@...ux.dev, daniel.lezcano@...aro.org, 
    tglx@...utronix.de, nick.hu@...ive.com, linux-riscv@...ts.infradead.org, 
    linux-kernel@...r.kernel.org, kvm@...r.kernel.org, 
    kvm-riscv@...ts.infradead.org
Subject: Re: [PATCH v3 0/3] riscv: fix timer update hazards on RV32

On Sun, 4 Jan 2026, Naohiko Shimizu wrote:

> This patch series fixes timer register update hazards on RV32 for
> clocksource, KVM, and suspend/resume paths by adopting the 3-step
> update sequence recommended by the RISC-V Privileged Specification.
> 
> Changes in v3:
> - Dropped redundant subject line from commit descriptions.
> - Added Fixes tags for all patches.
> - Moved Signed-off-by tags to the end of commit messages.
> 
> Changes in v2:
> - Added detailed architectural background to commit messages.
> - Added KVM and suspend/resume cases.
> 
> Naohiko Shimizu (3):
>   riscv: clocksource: Fix stimecmp update hazard on RV32
>   riscv: kvm: Fix vstimecmp update hazard on RV32
>   riscv: suspend: Fix stimecmp update hazard on RV32
> 
>  arch/riscv/kernel/suspend.c       | 3 ++-
>  arch/riscv/kvm/vcpu_timer.c       | 6 ++++--
>  drivers/clocksource/timer-riscv.c | 3 ++-
>  3 files changed, 8 insertions(+), 4 deletions(-)

Thanks, queued for v6.19-rc. 


- Paul

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