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Message-Id: <20260115-atlantis-clocks-v1-5-7356e671f28b@oss.tenstorrent.com>
Date: Thu, 15 Jan 2026 17:42:04 -0600
From: Anirudh Srinivasan <asrinivasan@....tenstorrent.com>
To: Drew Fustini <dfustini@....tenstorrent.com>, 
 Joel Stanley <jms@....tenstorrent.com>, Rob Herring <robh@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, 
 Michael Turquette <mturquette@...libre.com>, 
 Stephen Boyd <sboyd@...nel.org>, 
 Anirudh Srinivasan <asrinivasan@....tenstorrent.com>, 
 Philipp Zabel <p.zabel@...gutronix.de>
Cc: linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org, 
 linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org, joel@....id.au, 
 fustini@...nel.org, mpe@...nel.org, mpe@....tenstorrent.com, 
 npiggin@....tenstorrent.com, agross@...nel.org, agross@....tenstorrent.com
Subject: [PATCH 5/8] soc: tenstorrent: Add rcpu syscon reset register
 definitions

Document register offsets used for resets in Atlantis

Signed-off-by: Anirudh Srinivasan <asrinivasan@....tenstorrent.com>
---
 include/soc/tenstorrent/atlantis-syscon.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/include/soc/tenstorrent/atlantis-syscon.h b/include/soc/tenstorrent/atlantis-syscon.h
index b15dabfb42b5..f1dc6ad33c6d 100644
--- a/include/soc/tenstorrent/atlantis-syscon.h
+++ b/include/soc/tenstorrent/atlantis-syscon.h
@@ -19,6 +19,13 @@
 #define PLL_NOCC_EN_REG 0x120
 #define BUS_CG_REG 0x01FC
 
+/* RCPU Reset Register Offsets */
+#define RCPU_BLK_RST_REG 0x1c
+#define LSIO_BLK_RST_REG 0x20
+#define HSIO_BLK_RST_REG 0x0c
+#define PCIE_SUBS_RST_REG 0x00
+#define MM_RSTN_REG 0x14
+
 /* PLL Bit Definitions */
 #define PLL_CFG_EN_BIT BIT(0)
 #define PLL_CFG_BYPASS_BIT BIT(1)

-- 
2.43.0


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