linux-kernel - Re: [PATCH v4 3/4] arm64: dts: qcom: Introduce Glymur base dtsi

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Message-ID: <5a4e4b31-ca1b-4aae-b175-ee4ed692ea48@kernel.org>
Date: Thu, 15 Jan 2026 08:51:42 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Pankaj Patil <pankaj.patil@....qualcomm.com>,
 Bjorn Andersson <andersson@...nel.org>,
 Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org,
 Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>,
 Maulik Shah <maulik.shah@....qualcomm.com>,
 Sibi Sankar <sibi.sankar@....qualcomm.com>,
 Taniya Das <taniya.das@....qualcomm.com>,
 Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>,
 Qiang Yu <qiang.yu@....qualcomm.com>,
 Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>,
 Jishnu Prakash <jishnu.prakash@....qualcomm.com>,
 Abel Vesa <abelvesa@...nel.org>
Subject: Re: [PATCH v4 3/4] arm64: dts: qcom: Introduce Glymur base dtsi

On 12/01/2026 13:22, Pankaj Patil wrote:
> Introduce the base device tree support for Glymur – Qualcomm's
> next-generation compute SoC. The new glymur.dtsi describes the core SoC
> components, including:
> 
> - CPUs and CPU topology
> - Interrupt controller and TLMM
> - GCC,DISPCC and RPMHCC clock controllers
> - Reserved memory and interconnects
> - APPS and PCIe SMMU and firmware SCM
> - Watchdog, RPMHPD, APPS RSC and SRAM
> - PSCI and PMU nodes
> - QUPv3 serial engines
> - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS
> - PDP0 mailbox, IPCC and AOSS
> - Display clock controller
> - SPMI PMIC arbiter with SPMI0/1/2 buses
> - SMP2P nodes
> - TSENS and thermal zones (8 instances, 92 sensors)
> 
> Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104,
> PMH0110 along with temp-alarm and GPIO nodes needed on Glymur
> 
> Enabled PCIe controllers and associated PHY to support boot to
> shell with nvme storage,
> List of PCIe instances enabled:
> 
> - PCIe3b
> - PCIe4
> - PCIe5
> - PCIe6
> 
> Co-developed-by: Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>
> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>
> Co-developed-by: Maulik Shah <maulik.shah@....qualcomm.com>
> Signed-off-by: Maulik Shah <maulik.shah@....qualcomm.com>
> Co-developed-by: Sibi Sankar <sibi.sankar@....qualcomm.com>
> Signed-off-by: Sibi Sankar <sibi.sankar@....qualcomm.com>
> Co-developed-by: Taniya Das <taniya.das@....qualcomm.com>
> Signed-off-by: Taniya Das <taniya.das@....qualcomm.com>
> Co-developed-by: Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>
> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>
> Co-developed-by: Qiang Yu <qiang.yu@....qualcomm.com>
> Signed-off-by: Qiang Yu <qiang.yu@....qualcomm.com>
> Co-developed-by: Abel Vesa <abel.vesa@...aro.org>
> Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
> Co-developed-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>
> Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>
> Co-developed-by: Jishnu Prakash <jishnu.prakash@....qualcomm.com>
> Signed-off-by: Jishnu Prakash <jishnu.prakash@....qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@....qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/glymur.dtsi         | 5919 ++++++++++++++++++++++++++
>  arch/arm64/boot/dts/qcom/pmcx0102.dtsi       |  107 +
>  arch/arm64/boot/dts/qcom/pmh0101.dtsi        |   45 +
>  arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi |   83 +
>  arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi |   83 +
>  arch/arm64/boot/dts/qcom/pmk8850.dtsi        |   70 +
>  arch/arm64/boot/dts/qcom/smb2370.dtsi        |   45 +
>  7 files changed, 6352 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> new file mode 100644
> index 000000000000..91e577bd152f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -0,0 +1,5919 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <dt-bindings/clock/qcom,glymur-dispcc.h>
> +#include <dt-bindings/clock/qcom,glymur-gcc.h>
> +#include <dt-bindings/clock/qcom,glymur-tcsr.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/dma/qcom-gpi.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interconnect/qcom,icc.h>
> +#include <dt-bindings/interconnect/qcom,glymur-rpmh.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/mailbox/qcom-ipcc.h>
> +#include <dt-bindings/phy/phy-qcom-qmp.h>
> +#include <dt-bindings/power/qcom,rpmhpd.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +#include <dt-bindings/spmi/spmi.h>
> +
> +#include "glymur-ipcc.h"
> +
> +/ {
> +	interrupt-parent = <&intc>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "qcom,oryon";

Just to remind, this is not the correct compatible which we already
pointed out in the past. I am going to mark it as deprecated, so please
do not use it in the new code.

Best regards,
Krzysztof