linux-kernel - linux-next: manual merge of the cxl tree with the cxl-fixes tree

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Message-ID: <aWo3Xj3WU6Rqav5m@sirena.org.uk>
Date: Fri, 16 Jan 2026 13:04:30 +0000
From: Mark Brown <broonie@...nel.org>
To: Dan Williams <dan.j.williams@...el.com>,
	Dave Jiang <dave.jiang@...el.com>
Cc: Alison Schofield <alison.schofield@...el.com>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	Linux Next Mailing List <linux-next@...r.kernel.org>,
	Robert Richter <rrichter@....com>
Subject: linux-next: manual merge of the cxl tree with the cxl-fixes tree

Hi all,

Today's linux-next merge of the cxl tree got a conflict in:

  drivers/cxl/core/region.c

between commit:

  8441c7d3bd6c5 ("cxl: Check for invalid addresses returned from translation functions on errors")

from the cxl-fixes tree and commit:

  7af987b3f875c ("cxl/region: Translate DPA->HPA in unaligned MOD3 regions")

from the cxl tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

diff --cc drivers/cxl/core/region.c
index 5bd1213737fa2,8ed66bedb407e..0000000000000
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@@ -3116,9 -3247,11 +3247,11 @@@ u64 cxl_dpa_to_hpa(struct cxl_region *c
  		   u64 dpa)
  {
  	struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent);
+ 	struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
  	struct cxl_region_params *p = &cxlr->params;
  	struct cxl_endpoint_decoder *cxled = NULL;
 -	u64 dpa_offset, hpa_offset, hpa;
 +	u64 base, dpa_offset, hpa_offset, hpa;
+ 	bool unaligned = false;
  	u16 eig = 0;
  	u8 eiw = 0;
  	int pos;
@@@ -3132,21 -3265,32 +3265,38 @@@
  	if (!cxled)
  		return ULLONG_MAX;
  
- 	pos = cxled->pos;
- 	ways_to_eiw(p->interleave_ways, &eiw);
- 	granularity_to_eig(p->interleave_granularity, &eig);
- 
 -	dpa_offset = dpa - cxl_dpa_resource_start(cxled);
 +	base = cxl_dpa_resource_start(cxled);
 +	if (base == RESOURCE_SIZE_MAX)
 +		return ULLONG_MAX;
 +
 +	dpa_offset = dpa - base;
+ 
+ 	/* Unaligned calc for MOD3 interleaves not hbiw * 256MB aligned */
+ 	unaligned = region_is_unaligned_mod3(cxlr);
+ 	if (unaligned) {
+ 		hpa = unaligned_dpa_to_hpa(cxld, p, cxled->pos, dpa_offset);
+ 		if (hpa == ULLONG_MAX)
+ 			return ULLONG_MAX;
+ 
+ 		goto skip_aligned;
+ 	}
+ 	/*
+ 	 * Aligned calc for all power-of-2 interleaves and for MOD3
+ 	 * interleaves that are aligned at hbiw * 256MB
+ 	 */
+ 	pos = cxled->pos;
+ 	ways_to_eiw(p->interleave_ways, &eiw);
+ 	granularity_to_eig(p->interleave_granularity, &eig);
+ 
  	hpa_offset = cxl_calculate_hpa_offset(dpa_offset, pos, eiw, eig);
 +	if (hpa_offset == ULLONG_MAX)
 +		return ULLONG_MAX;
  
  	/* Apply the hpa_offset to the region base address */
- 	hpa = hpa_offset + p->res->start + p->cache_size;
+ 	hpa = hpa_offset + p->res->start;
+ 
+ skip_aligned:
+ 	hpa += p->cache_size;
  
  	/* Root decoder translation overrides typical modulo decode */
  	if (cxlrd->ops.hpa_to_spa)
@@@ -3197,15 -3379,16 +3389,19 @@@ static int region_offset_to_dpa_result(
  	 * CXL HPA is assumed to equal SPA.
  	 */
  	if (cxlrd->ops.spa_to_hpa) {
 -		hpa = cxlrd->ops.spa_to_hpa(cxlrd, p->res->start + offset);
 -		hpa_offset = hpa - p->res->start;
 -	} else {
 -		hpa_offset = offset;
 +		hpa_offset = cxlrd->ops.spa_to_hpa(cxlrd, p->res->start + offset);
 +		if (hpa_offset == ULLONG_MAX) {
 +			dev_dbg(&cxlr->dev, "HPA not found for %pr offset %#llx\n",
 +				p->res, offset);
 +			return -ENXIO;
 +		}
 +		hpa_offset -= p->res->start;
  	}
  
+ 	if (region_is_unaligned_mod3(cxlr))
+ 		return unaligned_region_offset_to_dpa_result(cxlr, offset,
+ 							     result);
+ 
  	pos = cxl_calculate_position(hpa_offset, eiw, eig);
  	if (pos < 0 || pos >= p->nr_targets) {
  		dev_dbg(&cxlr->dev, "Invalid position %d for %d targets\n",

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