lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <9c1b12fb-2c30-4610-8262-5c615e1ac982@kernel.org>
Date: Fri, 16 Jan 2026 15:28:33 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: "Lad, Prabhakar" <prabhakar.csengg@...il.com>,
 Conor Dooley <conor@...nel.org>, Linus Walleij <linus.walleij@...aro.org>,
 Geert Uytterhoeven <geert+renesas@...der.be>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, Magnus Damm <magnus.damm@...il.com>,
 linux-renesas-soc@...r.kernel.org, linux-gpio@...r.kernel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 Biju Das <biju.das.jz@...renesas.com>,
 Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
 Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: renesas,r9a09g077: Document pin
 configuration properties

On 14/01/2026 21:53, Lad, Prabhakar wrote:
>>>>> What are the meanings of "0" and "1" for slew rate? Why isn't this given
>>>> I'll add a description for it (0 = slow, 1 = fast) and the same values
>>>> are programmed in the register to configure the slew rate.
>>>>
>>>>> as the actual rates? The docs surely give more detail than just "slow"
>>>>> and "fast".
>>>> You mean to represent slew-rate in some sort of a unit?
>>>>
>>> Based on the comments from the HW team, there is no numerical
>>> definition to represent slow/fast It only defines a relative
>>> relationship.
>>>>>
>>>>>> +      renesas,drive-strength:
>>>>>> +        description:
>>>>>> +          Drive strength configuration value. Valid values are 0 to 3, representing
>>>>>> +          increasing drive strength from low, medium, high and ultra high.
>>>>>
> I got the feedback from the HW team "The RZ/T2H drive strength
> (driving ability) is expressed using abstract levels such as Low,
> Middle, and High. These values do not correspond directly to specific

Hold my beer and let me design PCB... I will use high voltage power
supply, then small resistor and small capacitor. Ah, and that regulator
here should operate on medium/middle voltage. Looks about right, all
ready to send to fab!

> mA units. To determine how much current the pin can actually drive,
> the engineer must refer to the electrical characteristics table.
> Therefore, the drive strength in RZ/T2H is a parameter that switches
> the internal output transistor mode rather than directly representing
> a physical drive current.
> Consequently, expressing RZ/T2H drive strength in milli- or
> micro-amps, as suggested by the reviewer, is inappropriate. To
> accurately reflect the SoC's hardware specification, introducing a
> custom property is essential."

So the hardware team tells you how you should model DT - "introducing a
custom property is essential".

That's pretty bold statement and very poor language construct. It is not
hardware team which decides how DT should be written.


Best regards,
Krzysztof

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ