linux-kernel - [PATCH 2/5] arm64: dts: qcom: milos: Split up uart11 pinctrl

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Message-Id: <20260116-milos-fp6-bt-wifi-v1-2-27b4fbb77e9c@fairphone.com>
Date: Fri, 16 Jan 2026 15:50:48 +0100
From: Luca Weiss <luca.weiss@...rphone.com>
To: Bjorn Andersson <andersson@...nel.org>, 
 Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, Alexander Koskovich <AKoskovich@...me>
Cc: ~postmarketos/upstreaming@...ts.sr.ht, phone-devel@...r.kernel.org, 
 linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org, 
 devicetree@...r.kernel.org, Luca Weiss <luca.weiss@...rphone.com>
Subject: [PATCH 2/5] arm64: dts: qcom: milos: Split up uart11 pinctrl

In order to set the pinctrl for the individual CTS, RTS, TX and RX pins,
split up the pinctrl configuration into 4 nodes so that boards can set
some properties separately.

Signed-off-by: Luca Weiss <luca.weiss@...rphone.com>
---
 arch/arm64/boot/dts/qcom/milos.dtsi | 26 +++++++++++++++-----------
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
index 0f69deabb60c..024e1c9992fe 100644
--- a/arch/arm64/boot/dts/qcom/milos.dtsi
+++ b/arch/arm64/boot/dts/qcom/milos.dtsi
@@ -915,7 +915,7 @@ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
 				interconnect-names = "qup-core",
 						     "qup-config";
 
-				pinctrl-0 = <&qup_uart11_default>, <&qup_uart11_cts_rts>;
+				pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
 				pinctrl-names = "default";
 
 				status = "disabled";
@@ -1835,20 +1835,24 @@ qup_uart5_default: qup-uart5-default-state {
 				bias-disable;
 			};
 
-			qup_uart11_default: qup-uart11-default-state {
-				/* TX, RX */
-				pins = "gpio50", "gpio51";
+			qup_uart11_cts: qup-uart11-cts-state {
+				pins = "gpio48";
 				function = "qup1_se4";
-				drive-strength = <2>;
-				bias-pull-up;
 			};
 
-			qup_uart11_cts_rts: qup-uart11-cts-rts-state {
-				/* CTS, RTS */
-				pins = "gpio48", "gpio49";
+			qup_uart11_rts: qup-uart11-rts-state {
+				pins = "gpio49";
+				function = "qup1_se4";
+			};
+
+			qup_uart11_tx: qup-uart11-tx-state {
+				pins = "gpio50";
+				function = "qup1_se4";
+			};
+
+			qup_uart11_rx: qup-uart11-rx-state {
+				pins = "gpio51";
 				function = "qup1_se4";
-				drive-strength = <2>;
-				bias-pull-down;
 			};
 
 			sdc2_default: sdc2-default-state {

-- 
2.52.0