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Message-ID: <CAL_JsqLffH-MY+6frA_kxwifUPskLY8eNqtBoOP0O7Dxs=XHLQ@mail.gmail.com>
Date: Fri, 16 Jan 2026 10:02:51 -0600
From: Rob Herring <robh@...nel.org>
To: Sjoerd Simons <sjoerd@...labora.com>
Cc: Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
Ryder Lee <ryder.lee@...iatek.com>, Jianjun Wang <jianjun.wang@...iatek.com>,
Bjorn Helgaas <bhelgaas@...gle.com>, Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof Wilczyński <kwilczynski@...nel.org>,
Manivannan Sadhasivam <mani@...nel.org>, Chunfeng Yun <chunfeng.yun@...iatek.com>,
Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>, Lee Jones <lee@...nel.org>,
Andrew Lunn <andrew+netdev@...n.ch>, "David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Lorenzo Bianconi <lorenzo@...nel.org>, Felix Fietkau <nbd@....name>, kernel@...labora.com,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-mediatek@...ts.infradead.org,
linux-pci@...r.kernel.org, linux-phy@...ts.infradead.org,
netdev@...r.kernel.org, Daniel Golle <daniel@...rotopia.org>,
Bryan Hinton <bryan@...anhinton.com>
Subject: Re: [PATCH v5 2/8] arm64: dts: mediatek: mt7981b: Add PCIe and USB support
On Tue, Dec 23, 2025 at 6:38 AM Sjoerd Simons <sjoerd@...labora.com> wrote:
>
> Add device tree nodes for PCIe controller and USB3 XHCI host
> controller on MT7981B SoC. Both controllers share the USB3 PHY
> which can be configured for either USB3 or PCIe operation.
>
> The USB3 XHCI controller supports USB 2.0 and USB 3.0 SuperSpeed
> operation. The PCIe controller is compatible with PCIe Gen2
> specifications.
>
> Also add the topmisc syscon node required for USB/PCIe PHY
> multiplexing.
>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
> Signed-off-by: Sjoerd Simons <sjoerd@...labora.com>
> ---
> V1 -> V2: Keep xhci reg and phys properties in single lines
> ---
> arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 80 +++++++++++++++++++++++++++++++
> 1 file changed, 80 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi
> index 416096b80770..d3f37413413e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi
> @@ -2,6 +2,7 @@
>
> #include <dt-bindings/clock/mediatek,mt7981-clk.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/phy/phy.h>
> #include <dt-bindings/reset/mt7986-resets.h>
>
> / {
> @@ -223,6 +224,55 @@ auxadc: adc@...0d000 {
> status = "disabled";
> };
>
> + xhci: usb@...00000 {
> + compatible = "mediatek,mt7986-xhci", "mediatek,mtk-xhci";
> + reg = <0 0x11200000 0 0x2e00>, <0 0x11203e00 0 0x0100>;
> + reg-names = "mac", "ippc";
> + clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
> + <&infracfg CLK_INFRA_IUSB_CK>,
> + <&infracfg CLK_INFRA_IUSB_133_CK>,
> + <&infracfg CLK_INFRA_IUSB_66M_CK>,
> + <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
> + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
> + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
> + status = "disabled";
> + };
> +
> + pcie: pcie@...80000 {
> + compatible = "mediatek,mt7981-pcie",
> + "mediatek,mt8192-pcie";
> + reg = <0 0x11280000 0 0x4000>;
> + reg-names = "pcie-mac";
> + ranges = <0x82000000 0 0x20000000
> + 0x0 0x20000000 0 0x10000000>;
> + bus-range = <0x00 0xff>;
> + clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
> + <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
> + <&infracfg CLK_INFRA_IPCIER_CK>,
> + <&infracfg CLK_INFRA_IPCIEB_CK>;
> + clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
> + device_type = "pci";
> + phys = <&u3port0 PHY_TYPE_PCIE>;
> + phy-names = "pcie-phy";
> + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie_intc 0>,
> + <0 0 0 2 &pcie_intc 1>,
> + <0 0 0 3 &pcie_intc 2>,
> + <0 0 0 4 &pcie_intc 3>;
> + #address-cells = <3>;
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + status = "disabled";
> +
> + pcie_intc: interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> pio: pinctrl@...00000 {
> compatible = "mediatek,mt7981-pinctrl";
> reg = <0 0x11d00000 0 0x1000>,
> @@ -252,6 +302,36 @@ mux {
> };
> };
>
> + topmisc: topmisc@...10000 {
> + compatible = "mediatek,mt7981-topmisc", "syscon";
> + reg = <0 0x11d10000 0 0x10000>;
> + #clock-cells = <1>;
This is now a warning as the syscon.yaml binding this compatible is
defined in doesn't allow #clock-cells.
Rob
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