linux-kernel - Re: [PATCH v6 5/5] iio: adc: ad7768-1: add support for ADAQ776x-1 ADC Family

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Message-ID: <20260116185200.38be8bc7@jic23-huawei>
Date: Fri, 16 Jan 2026 18:52:00 +0000
From: Jonathan Cameron <jic23@...nel.org>
To: Jonathan Santos <Jonathan.Santos@...log.com>
Cc: <linux-iio@...r.kernel.org>, <devicetree@...r.kernel.org>,
 <linux-kernel@...r.kernel.org>, <lars@...afoo.de>,
 <Michael.Hennerich@...log.com>, <dlechner@...libre.com>,
 <nuno.sa@...log.com>, <andy@...nel.org>, <robh@...nel.org>,
 <krzk+dt@...nel.org>, <conor+dt@...nel.org>, <jonath4nns@...il.com>
Subject: Re: [PATCH v6 5/5] iio: adc: ad7768-1: add support for ADAQ776x-1
 ADC Family

On Wed, 14 Jan 2026 06:27:29 -0300
Jonathan Santos <Jonathan.Santos@...log.com> wrote:

> Add support for ADAQ7767/68/69-1 series, which includes PGIA and
> Anti-aliasing filter (AAF) gains. Unlike the AD7768-1, they do not
> provide a VCM regulator interface.
> 
> The PGA gain is configured in run-time through the scale attribute,
> if supported by the device. PGA is controlled by GPIOs provided in
> the device tree.
> 
> The AAF gain is defined by hardware connections and should be specified
> in the device tree.
> 
> Signed-off-by: Jonathan Santos <Jonathan.Santos@...log.com>
Hi Jonathan,

See inline.  One small thing I am fine fixing up whilst applying
if nothing else comes up.

thanks,

Jonathan



> ---

> diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c
> index bd4b2e090c5b..980c079ab41a 100644
> --- a/drivers/iio/adc/ad7768-1.c
> +++ b/drivers/iio/adc/ad7768-1.c
> +static void ad7768_fill_scale_tbl(struct iio_dev *dev)
> +{
> +	struct ad7768_state *st = iio_priv(dev);
> +	const struct iio_scan_type *scan_type;
> +	int val, val2, tmp0, tmp1, i;
> +	struct u32_fract fract;
> +	unsigned long n, d;
> +	u64 tmp2;
> +
> +	scan_type = iio_get_current_scan_type(dev, &dev->channels[0]);
> +	if (scan_type->sign == 's')
> +		val2 = scan_type->realbits - 1;
> +	else
> +		val2 = scan_type->realbits;
> +
> +	for (i = 0; i < st->chip->num_pga_modes; i++) {
> +		/* Convert gain to a fraction format */
> +		fract.numerator = st->chip->pga_gains[i];
> +		fract.denominator = MILLI;
> +		if (st->chip->has_variable_aaf) {
> +			fract.numerator *= ad7768_aaf_gains_bp[st->aaf_gain];
> +			fract.denominator *= PERMYRIAD;
> +		}
> +
> +		rational_best_approximation(fract.numerator, fract.denominator,
> +					    INT_MAX, INT_MAX, &n, &d);
> +
> +		val = mult_frac(st->vref_uv, d, n);
> +		/* Would multiply by NANO here, but value is already in milli */
> +		tmp2 = ((u64)val * MICRO) >> val2;
> +		tmp0 = div_u64_rem(tmp2, NANO, &tmp1);
> +		st->scale_tbl[i][0] = tmp0; /* Integer part */
> +		st->scale_tbl[i][1] = abs(tmp1); /* Fractional part */

How does remainder from div_u64_rem() end up other than positive?
That divides a u64 by a u32 and takes a u32 * for that final parameter.
Changing the type of tmp1 to u32 should do the job. Given we do the divisor
is big enough, this can't be something subtle with the top bit set
(if it were it would need a comment!)

If nothing else comes up I can do that whilst applying
(I'll wait on Andy having a chance to sanity check the PERMYRIAD stuff anyway).

> +	}
> +}
> +