From 793171b857a7c37c838d882b2610b89d6ef90e1a Mon Sep 17 00:00:00 2001 From: Gokul Praveen Date: Fri, 16 Jan 2026 14:31:02 +0530 Subject: [PATCH] Debug prints to check if period and duty cycle is reflected or not Signed-off-by: Gokul Praveen --- drivers/pwm/pwm-tiehrpwm.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index 7a86cb090f76..3626375c5e4a 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -283,6 +283,7 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, ehrpwm_write(pc->mmio_base, TBPRD, period_cycles - 1); + /* Configure ehrpwm counter for up-count mode */ ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK, TBCTL_CTRMODE_UP); @@ -290,7 +291,15 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, if (!(duty_cycles > period_cycles)) ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles); + u16 duty_cycle = ehrpwm_read(pc->mmio_base, CMPB); + u16 period = ehrpwm_read(pc->mmio_base, TBPRD); + + printk("Before put sync: Period:%u, Duty cycle:%u\n",(unsigned int)period,(unsigned int)duty_cycle); pm_runtime_put_sync(pwmchip_parent(chip)); + + //duty_cycle = ehrpwm_read(pc->mmio_base, CMPB); + //period = ehrpwm_read(pc->mmio_base, TBPRD); + //printk("After put sync: Period:%d, Duty cycle:%d\n",period,duty_cycle); return 0; } @@ -304,6 +313,10 @@ static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) /* Leave clock enabled on enabling PWM */ pm_runtime_get_sync(pwmchip_parent(chip)); + u16 duty_cycle = ehrpwm_read(pc->mmio_base, CMPB); + u16 period = ehrpwm_read(pc->mmio_base, TBPRD); + printk("EHRPWM enable function: Period:%u, Duty cycle:%u\n",(unsigned int)period,(unsigned int)duty_cycle); + /* Disabling Action Qualifier on PWM output */ if (pwm->hwpwm) { aqcsfrc_val = AQCSFRC_CSFB_FRCDIS; @@ -327,6 +340,7 @@ static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) return ret; } + return 0; } -- 2.34.1