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Message-ID: <CAMuHMdUqWUriQHR8UY631HZfVNsejgXE64jrChi=k2=5E6Hi-Q@mail.gmail.com>
Date: Fri, 16 Jan 2026 11:07:03 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Miquel Raynal <miquel.raynal@...tlin.com>
Cc: Mark Brown <broonie@...nel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Geert Uytterhoeven <geert+renesas@...der.be>, Magnus Damm <magnus.damm@...il.com>, 
	Vaishnav Achath <vaishnav.a@...com>, Thomas Petazzoni <thomas.petazzoni@...tlin.com>, 
	Hervé Codina <herve.codina@...tlin.com>, 
	Wolfram Sang <wsa+renesas@...g-engineering.com>, Vignesh Raghavendra <vigneshr@...com>, 
	Santhosh Kumar K <s-k6@...com>, Pratyush Yadav <pratyush@...nel.org>, 
	Pascal Eberhard <pascal.eberhard@...com>, linux-spi@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	linux-renesas-soc@...r.kernel.org
Subject: Re: [PATCH v2 13/13] ARM: dts: r9a06g032: Describe the QSPI controller

Hi Miquel,

On Fri, 16 Jan 2026 at 10:49, Miquel Raynal <miquel.raynal@...tlin.com> wrote:
> >> +               qspi0: spi@...05000 {
> >> +                       compatible = "renesas,r9a06g032-qspi", "renesas,rzn1-qspi", "cdns,qspi-nor";
> >> +                       reg = <0x40005000 0x1000>, <0x10000000 0x10000000>;
> >> +                       interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> >> +                       clocks = <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSPI0>,
> >> +                                <&sysctrl R9A06G032_HCLK_QSPI0>;
> >> +                       clock-names = "ref", "ahb", "apb";
> >> +                       #address-cells = <1>;
> >> +                       #size-cells = <0>;
> >> +                       cdns,fifo-width = <4>;
> >
> > <4> is the default, right?
>
> It is the default in the bindings indeed, however the driver does not
> imply that default and errors out if the property is missing. The
> property is also marked required in the bindings, which is kind of
> incorrect I guess. Also, all DTS explicitly set this value to 4.

OK.

>
> However looking into the RM I found "Transmit and receive FIFOs are 16
> bytes". I haven't tested that, I will.

Oh, that bullet is not present in the docs on the CD I looked at.
It is indeed documented in newer versions.

There's also cdns,fifo-depth, which thus should be 4?

>
> >> +                       cdns,trigger-address = <0>;
> >
> > Where in the RZ/N1 docs can I find if these two properties are
> > correct?
>
> This property is mandatory. Maybe I could just discard it for my
> compatible, because it is only relevant for indirect modes, which are
> unsupported.

OK.

> >> +                       status = "disabled";
> >> +               };
> >> +
> >>                 rtc0: rtc@...06000 {
> >>                         compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
> >>                         reg = <0x40006000 0x1000>;
> >
> > The rest LGTM, ignoring my comments on the bindings:
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
>
> Thanks for the review, but I guess if I end up changing the DTS snippet
> I might drop it. Or would you like me to keep it anyway?

Please keep it as long as you don't change the (SoC integration)
things I typically focus on (address, interrupts, clocks), and don't make
too wild changes ;-)

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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