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Message-ID: <aWrVplD0jfx-JM1v@orome>
Date: Sat, 17 Jan 2026 01:19:59 +0100
From: Thierry Reding <thierry.reding@...il.com>
To: Svyatoslav Ryhel <clamor95@...il.com>
Cc: Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Thierry Reding <treding@...dia.com>, Jonathan Hunter <jonathanh@...dia.com>,
Prashant Gaikwad <pgaikwad@...dia.com>, Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Mikko Perttunen <mperttunen@...dia.com>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Dmitry Osipenko <digetx@...il.com>, Charan Pedumuru <charan.pedumuru@...il.com>,
devicetree@...r.kernel.org, linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, dri-devel@...ts.freedesktop.org
Subject: Re: [PATCH v2 1/4 RESEND] clk: tegra20: reparent dsi clock to
pll_d_out0
On Thu, Dec 04, 2025 at 08:17:00AM +0200, Svyatoslav Ryhel wrote:
> Reparent DSI clock to PLLD_OUT0 instead of directly descend from PLLD.
>
> Signed-off-by: Svyatoslav Ryhel <clamor95@...il.com>
> Acked-by: Stephen Boyd <sboyd@...nel.org>
> ---
> drivers/clk/tegra/clk-tegra20.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Applied, thanks.
Thierry
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