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Message-ID: <cover.1768624180.git.nicolinc@nvidia.com>
Date: Fri, 16 Jan 2026 20:56:39 -0800
From: Nicolin Chen <nicolinc@...dia.com>
To: <jgg@...dia.com>, <will@...nel.org>, <robin.murphy@....com>,
<bhelgaas@...gle.com>
CC: <joro@...tes.org>, <praan@...gle.com>, <baolu.lu@...ux.intel.com>,
<kevin.tian@...el.com>, <miko.lenczewski@....com>,
<linux-arm-kernel@...ts.infradead.org>, <iommu@...ts.linux.dev>,
<linux-kernel@...r.kernel.org>, <linux-pci@...r.kernel.org>
Subject: [PATCH RFCv1 0/3] Allow ATS to be always on for certain ATS-capable devices
PCI ATS function is controlled by IOMMU driver calling pci_enable_ats() and
pci_disable_ats() helpers. In general, IOMMU driver only enables ATS, when
a translation channel is enabled on a PASID, typically for an SVA use case.
When a device's RID is IOMMU bypassed and there is no active PASID running
SVA use case, ATS is always disabled.
However, certain pcie devices support non-PASID ATS on its RID, even if the
RID is IOMMU bypassed. E.g. CXL.cache capability requires ATS to access the
physical memory; some NVIDIA GPUs in non-CXL configuration also support ATS
on a bypassed RID.
Provide a helper function to detect CXL.cache capability and scan through a
device ID list.
As the initial use case, call the helper in ARM SMMUv3 driver and adapt the
driver accordingly with a per-device ats_always_on flag.
This is on Github:
https://github.com/nicolinc/iommufd/commits/pci_ats_always_on-rfcv1/
Nicolin Chen (3):
PCI: Allow ATS to be always on for CXL.cache capable devices
PCI: Allow ATS to be always on for non-CXL NVIDIA GPUs
iommu/arm-smmu-v3: Allow ATS to be always on
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 +
drivers/pci/pci.h | 9 +++
include/linux/pci-ats.h | 3 +
include/uapi/linux/pci_regs.h | 5 ++
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 74 ++++++++++++++++++---
drivers/pci/ats.c | 45 +++++++++++++
drivers/pci/quirks.c | 23 +++++++
7 files changed, 149 insertions(+), 11 deletions(-)
--
2.43.0
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