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Message-ID: <20260117101806.2172918-1-huangchenghai2@huawei.com>
Date: Sat, 17 Jan 2026 18:18:02 +0800
From: Chenghai Huang <huangchenghai2@...wei.com>
To: <herbert@...dor.apana.org.au>, <davem@...emloft.net>
CC: <linux-kernel@...r.kernel.org>, <linux-crypto@...r.kernel.org>,
<fanghao11@...wei.com>, <liulongfang@...wei.com>, <qianweili@...wei.com>,
<wangzhou1@...ilicon.com>
Subject: [PATCH 0/4] crypto: hisilicon/qm - fix several mailbox issues
These patchset fix several issues for mailbox handling in the
hisilicon/qm crypto accelerator driver:
1. Fix the memory barrier order in mailbox operations to ensure data is
up-to-date before hardware access.
2. Remove unnecessary architecture-related code, as the driver is
exclusively used on ARM64.
3. Use 128-bit atomic read to replace the current mailbox operations
in the driver. Since the PF and VFs share the mmio memory of the
mailbox, mailbox mmio memory access needs to be atomic. Because the
stp and ldp instructions do not guarantee atomic access to mmio memory
on all hardware, the current assembly implementation is placed in the
driver.
4. Increase the mailbox wait time for queue and function stop commands
to match the hardware processing timeout.
---
Chenghai Huang (1):
crypto: hisilicon/qm - move the barrier before writing to the mailbox
register
Weili Qian (3):
crypto: hisilicon/qm - remove unnecessary code in qm_mb_write()
crypto: hisilicon/qm - obtain the mailbox configuration at one time
crypto: hisilicon/qm - increase wait time for mailbox
drivers/crypto/hisilicon/qm.c | 177 +++++++++++++++++++++-------------
include/linux/hisi_acc_qm.h | 1 +
2 files changed, 113 insertions(+), 65 deletions(-)
--
2.33.0
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