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Message-ID: <20260117-upstream_sgpio-v1-0-850ef3ffb680@aspeedtech.com>
Date: Sat, 17 Jan 2026 19:17:07 +0800
From: Billy Tsai <billy_tsai@...eedtech.com>
To: Linus Walleij <linusw@...nel.org>, Bartosz Golaszewski <brgl@...nel.org>,
Joel Stanley <joel@....id.au>, Andrew Jeffery <andrew@...econstruct.com.au>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
CC: <linux-gpio@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
<linux-aspeed@...ts.ozlabs.org>, <linux-kernel@...r.kernel.org>, "Andrew
Jeffery" <andrew@...id.au>, <devicetree@...r.kernel.org>,
<bmc-sw@...eedtech.com>, Billy Tsai <billy_tsai@...eedtech.com>
Subject: [PATCH 0/5] Add Aspeed G7 sgpio support
The Aspeed 7th generation SoC features two SGPIO master controllers: both
with 256 serial inputs and outputs. The main difference from the previous
generation is that the control logic has been updated to support
per-pin control, allowing each pin to have its own 32-bit register for
configuring value, interrupt type, and more.
This patch serial also add low-level operations (llops) to abstract the
register access for SGPIO registers making it easier to extend the driver
to support different hardware register layouts.
Signed-off-by: Billy Tsai <billy_tsai@...eedtech.com>
---
Billy Tsai (5):
gpio: aspeed-sgpio: Change the macro to support deferred probe
gpio: aspeed-sgpio: Remove unused bank name field
gpio: aspeed-sgpio: Create llops to handle hardware access
dt-bindings: gpio: aspeed,sgpio: Support ast2700
gpio: aspeed-sgpio: Support G7 Aspeed sgpiom controller
.../devicetree/bindings/gpio/aspeed,sgpio.yaml | 4 +-
drivers/gpio/gpio-aspeed-sgpio.c | 364 +++++++++++++--------
2 files changed, 228 insertions(+), 140 deletions(-)
---
base-commit: dd9b004b7ff3289fb7bae35130c0a5c0537266af
change-id: 20251223-upstream_sgpio-70d815c64a19
Best regards,
--
Billy Tsai <billy_tsai@...eedtech.com>
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