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Message-ID: <6fd412e1-31d4-4f8b-9aa3-e2d7423fca66@linaro.org>
Date: Sat, 17 Jan 2026 21:45:31 +0000
From: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
To: david@...t.cz, Robert Foss <rfoss@...nel.org>,
Todor Tomov <todor.too@...il.com>,
Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Luca Weiss <luca.weiss@...rphone.com>, Petr Hodina <phodina@...tonmail.com>,
Casey Connolly <casey.connolly@...aro.org>, "Dr. Git" <drgitx@...il.com>
Cc: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
Joel Selvaraj <foss@...lselvaraj.com>, Kieran Bingham <kbingham@...nel.org>,
Sakari Ailus <sakari.ailus@...ux.intel.com>, linux-media@...r.kernel.org,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
phone-devel@...r.kernel.org
Subject: Re: [PATCH v3 4/8] media: qcom: camss: Initialize lanes after lane
configuration is available
On 17/01/2026 15:36, David Heidelberg via B4 Relay wrote:
> From: Petr Hodina <phodina@...tonmail.com>
>
> The lanes must not be initialized before the driver has access to
> the lane configuration, as it depends on whether D-PHY or C-PHY mode
> is in use. Move the lane initialization to a later stage where the
> configuration structures are available.
>
> Signed-off-by: Petr Hodina <phodina@...tonmail.com>
> Signed-off-by: David Heidelberg <david@...t.cz>
> ---
> .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 91 ++++++++++++++--------
> 1 file changed, 57 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> index f3a8625511e1e..9e8470358515f 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> @@ -1048,6 +1048,62 @@ static int csiphy_lanes_enable(struct csiphy_device *csiphy,
> u8 val;
> int i;
>
> + switch (csiphy->camss->res->version) {
> + case CAMSS_845:
> + { /* V4L2_MBUS_CSI2_DPHY */
> + regs->lane_regs = &lane_regs_sdm845[0];
> + regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
> + }
> + break;
> + case CAMSS_2290:
> + case CAMSS_6150:
> + { /* V4L2_MBUS_CSI2_DPHY */
> + regs->lane_regs = &lane_regs_qcm2290[0];
> + regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
> + }
> + break;
> + case CAMSS_7280:
> + case CAMSS_8250:
> + { /* V4L2_MBUS_CSI2_DPHY */
> + regs->lane_regs = &lane_regs_sm8250[0];
> + regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
> + }
> + break;
> + case CAMSS_8280XP:
> + { /* V4L2_MBUS_CSI2_DPHY */
> + regs->lane_regs = &lane_regs_sc8280xp[0];
> + regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
> + }
> + break;
> + case CAMSS_X1E80100:
> + { /* V4L2_MBUS_CSI2_DPHY */
> + regs->lane_regs = &lane_regs_x1e80100[0];
> + regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100);
> + }
> + break;
> + case CAMSS_8550:
> + { /* V4L2_MBUS_CSI2_DPHY */
> + regs->lane_regs = &lane_regs_sm8550[0];
> + regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
> + }
> + break;
> + case CAMSS_8650:
> + { /* V4L2_MBUS_CSI2_DPHY */
> + regs->lane_regs = &lane_regs_sm8650[0];
> + regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650);
> + }
> + break;
> + case CAMSS_8300:
> + case CAMSS_8775P:
> + { /* V4L2_MBUS_CSI2_DPHY */
> + regs->lane_regs = &lane_regs_sa8775p[0];
> + regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
> + }
> + break;
> + default:
> + break;
> + }
> +
> settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
>
> val = 0;
> @@ -1119,49 +1175,16 @@ static int csiphy_init(struct csiphy_device *csiphy)
> return -ENOMEM;
>
> csiphy->regs = regs;
> - regs->offset = 0x800;
> regs->common_status_offset = 0xb0;
>
> switch (csiphy->camss->res->version) {
> - case CAMSS_845:
> - regs->lane_regs = &lane_regs_sdm845[0];
> - regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
> - break;
> - case CAMSS_2290:
> - case CAMSS_6150:
> - regs->lane_regs = &lane_regs_qcm2290[0];
> - regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
> - break;
> - case CAMSS_7280:
> - case CAMSS_8250:
> - regs->lane_regs = &lane_regs_sm8250[0];
> - regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
> - break;
> - case CAMSS_8280XP:
> - regs->lane_regs = &lane_regs_sc8280xp[0];
> - regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
> - break;
> case CAMSS_X1E80100:
> - regs->lane_regs = &lane_regs_x1e80100[0];
> - regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100);
> - regs->offset = 0x1000;
> - break;
> case CAMSS_8550:
> - regs->lane_regs = &lane_regs_sm8550[0];
> - regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
> - regs->offset = 0x1000;
> - break;
> case CAMSS_8650:
> - regs->lane_regs = &lane_regs_sm8650[0];
> - regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650);
> regs->offset = 0x1000;
> break;
> - case CAMSS_8300:
> - case CAMSS_8775P:
> - regs->lane_regs = &lane_regs_sa8775p[0];
> - regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
> - break;
> default:
> + regs->offset = 0x800;
> break;
> }
>
>
Subject to testing.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
---
bod
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