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Message-Id: <20260117-misc_dts-v2-1-0f319c7e9b55@nxp.com>
Date: Sat, 17 Jan 2026 22:37:35 -0500
From: Frank Li <Frank.Li@....com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>, Nathan Chancellor <nathan@...nel.org>,
Nicolas Schier <nsc@...nel.org>
Cc: devicetree@...r.kernel.org, imx@...ts.linux.dev,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-kbuild@...r.kernel.org, Frank Li <Frank.Li@....com>
Subject: [PATCH v2 1/9] arm64: dts: imx8mm-evk: replace space with tab
Replace spaces with tabs to follow the coding style.
Signed-off-by: Frank Li <Frank.Li@....com>
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 38 +++++++++++++--------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index 6eab8a6001dbf9d88f1de93709faa3d82dc56da6..f58d849a8709485424d811f32f565590f2eb3f52 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -691,7 +691,7 @@ MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
pinctrl_ir: irgrp {
fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
+ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
>;
};
@@ -724,26 +724,26 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
pinctrl_pcie0: pcie0grp {
fsl,pins = <
- MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61
- MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
+ MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61
+ MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
>;
};
pinctrl_pcie0_reg: pcie0reggrp {
fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
+ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
- MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
- MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
- MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
- MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6
- MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6
- MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6
- MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6
+ MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
+ MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
+ MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
+ MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6
+ MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6
+ MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6
+ MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6
>;
};
@@ -761,19 +761,19 @@ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
pinctrl_sai2: sai2grp {
fsl,pins = <
- MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
- MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
- MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
- MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
+ MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
+ MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
+ MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
+ MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
- MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
- MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
- MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
- MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
+ MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
+ MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
+ MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
+ MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
>;
};
--
2.34.1
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