[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <aW5wnxDDVn2KoriB@arm.com>
Date: Mon, 19 Jan 2026 17:57:51 +0000
From: Catalin Marinas <catalin.marinas@....com>
To: Carl Worth <carl@...amperecomputing.com>
Cc: Will Deacon <will@...nel.org>, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, Taehyun Noh <taehyun@...xas.edu>
Subject: Re: [PATCH v2 2/2] arm64: mte: Set TCMA1 whenever MTE is present in
the kernel
On Thu, Jan 15, 2026 at 03:07:18PM -0800, Carl Worth wrote:
> Set the TCMA1 bit so that access to TTBR1 addresses with 0xf in their
> tag bits will be treated as tag unchecked.
>
> This is important to avoid unwanted tag checking on some
> systems. Specifically, SCTLR_EL1.TCF can be set to indicate that no
> tag check faults are desired. But the architecture doesn't guarantee
> that in this case the system won't still perform tag checks.
>
> Use TCMA1 to ensure that undesired tag checks are not performed. This
> bit was already set in the KASAN case. Adding it to the non-KASAN case
> prevents tag checking since all TTBR1 address will have a value of 0xf
> in their tag bits.
>
> This patch has been measured on an Ampere system to improve the following:
>
> * Eliminate over 98% of kernel-side tag checks during "perf bench
> futex hash", as measured with "perf stat".
>
> * Eliminate all MTE overhead (was previously a 25% performance
> penalty) from the Phoronix pts/memcached benchmark (1:10 Set:Get
> ration with 96 cores).
>
> Reported-by: Taehyun Noh <taehyun@...xas.edu>
> Suggested-by: Catalin Marinas <catalin.marinas@....com>
> Signed-off-by: Carl Worth <carl@...amperecomputing.com>
Thanks for testing an sending this.
Reviewed-by: Catalin Marinas <catalin.marinas@....com>
Powered by blists - more mailing lists